Seiko Epson Corporation

Seiko Espon Corporation

Takuya Ishida

Yoshiyuki Kamihara

Nobuyuki Saito

Tomonaga Hasegawa

Yukinari Shibata

Haruo Nishida

Fumitoshi Wada

Shoichiro Kasahara

Fumikazu Komatsu

Mitsuaki Sawada

Shun Oshita

Kenyou Nagao

Hiroaki Shimono

Takao Ogawa

Kanji Aoki

Nobuharu Kobayashi

Image data which defines an ink amount to be ejected from each of a plurality of nozzles is stored in memory, the image data which is stored in the memory is subjected to an interpolation process corresponding to a faulty nozzle of a print head, the image data which is subjected to the interpolation process is subjected to a rotation process and the image data which defines the ink amount to be ejected and corresponds to each of the plurality of nozzles to be stored in the memory so as to be in a read-out order of the memory when the print head is positioned at a certain point in relation to the print medium, and the image data which is subjected to the rotation process is read out and output as the print data.

Printing apparatus, control device, and image processing method

A data transfer control device includes an OUT-transfer transmitter circuit which transmits OUT data by driving a serial signal line, a clock-transfer transmitter circuit which transmits a clock signal CLK by driving a serial signal line, a PLL circuit which generates the clock signal CLK, and a power-down setting circuit which sets a power-down mode. In a first power-down mode, the OUT-transfer transmitter circuit is set to the power-down mode, and the clock-transfer transmitter circuit is set to the power-down mode to stop a system clock signal of a target-side data transfer control device. In a second power-down mode, the OUT-transfer transmitter circuit is set to the power-down mode without setting the clock-transfer transmitter circuit to the power-down mode.

Data transfer control device and electronic instrument

An integrated circuit device includes a common transceiver macrocell including a circuit necessary for host operation and a circuit necessary for device operation. The common transceiver macrocell includes an analog front-end circuit and a high-speed logic circuit. The high-speed logic circuit includes a parallel/serial conversion circuit, a first parallel interface which serves as an interface between an external circuit and the parallel/serial conversion circuit, a sampling clock generation circuit, a serial/parallel conversion circuit, and a second parallel interface which serves as an interface between the serial/parallel conversion circuit and the external circuit.

Integrated circuit device and electronic instrument

A receiver circuit includes: a current/voltage conversion circuit which performs a current/voltage conversion based on current which flows through the differential signal lines and outputs voltage signals; a comparator which compares the voltage signals and outputs an output signal; a power-down detection circuit which, when the transmitter circuit transmits a power-down command by current-driving the differential signal lines in a normal transfer mode, detects the transmitted power-down command based on a comparison result from the comparator; and a power-down setting circuit which sets at least one of the current/voltage conversion circuit and the comparator to a power-down mode when the power-down command is detected.

Receiver circuit, interface circuit, and electronic instrument

A transceiver includes upstream differential signal lines DPUP and DMUP, downstream differential signal lines DPDW and DMDW, common differential signal lines DPCM and DMCM, a first transmission driver of which outputs are connected to DPUP and DMUP, a second transmission driver of which outputs are connected to DPDW and DMDW, a first switch circuit which connects the first transmission driver to a logic circuit during upstream connection and connects the second transmission driver to the logic circuit during downstream connection, a second switch circuit which respectively connects DPUP and DMUP to DPCM and DMCM during the upstream connection and respectively connects DPDW and DMDW to DPCM and DMCM during the downstream connection, and a third transmission driver connected to DPCM and DMCM.

Transceiver, data transfer control device, and electronic instrument

An objective of the present invention is to provide a data transfer control device and electronic equipment which make it possible to reduce processing overheads in the firmware and implement high-speed data transfer. In a data transfer control device in accordance with the IEEE 1394 standard, the header of a packet is written to a header area, the ORB (data for SBP-2) of the packet is written to an ORB area, and the stream (data for the application layer) of the packet is written to a stream area. The stream area is managed by hardware in accordance with full and empty signals. Indication information is comprised within a transaction label tl of a request packet, and the header, ORB, and stream of a response packet are written to areas indicated by the indication information comprised within tl, when the response packet is received. The device is also provided with registers TSR and TER that contain addresses TS and TE for securing a transmission area in the stream area and registers RSR and RER that contain addresses RS and RE for securing a reception area therein.

Data transfer control device and electronic equipment

A transfer controller (or a host controller) issues IN tokens to a plurality of USB devices connected to USB and including first and second USB devices. When data including destination information which specifies the second USB device as a destination has been received in response to an IN token issued to the first USB device, the transfer controller issues an OUT token to the second USB device and transmits the received data from the first USB device to the second USB device. The transfer controller issues an IN token to at least one of the USB devices which has declared itself to be a local area network (LAN) node.

USB data transfer control device including first and second USB device wherein destination information about second device is sent by first device

A transaction is automatically issued with respect to one of end points and data is automatically transferred while the remaining data size of the transfer data is calculated based on the total size and the maximum packet size. When the remaining data size in the current transaction is less than the maximum packet size, the next transaction is issued automatically, and a short packet is transferred automatically to nest one of the end points. When the payload size of the packet to be transferred by the current transaction is the maximum packet size and the remaining data size of the transfer data is zero, a short packet of zero data length is transferred automatically to the next one of the end points. When DMA transfer is complete and the remaining data to be transferred is zero, a short packet of zero data length is transferred automatically in response to an IN token from a host. Data transfer according to USB On-The-Go is performed.

Data transfer control device, electronic equipment, and data transfer control method

A macro block MBincluding a physical-layer circuit PHY for communications performs transmission and reception processing to and from a macro block MBat a clock frequency CF. A test circuit TC includes a test transmission buffer TXB that stores a transmission data signal from a test input terminal TPI at a frequency CFthat is lower than the frequency CF, and a test reception buffer RXB that outputs a reception data signal to a test output terminal TPO at a frequency CFthat is lower than the frequency CF. After the transmission buffer TXB has stored the transmission data signal from the terminal TPI at the frequency CF, it outputs the stored transmission data signal to the MBat the frequency CF. After the reception buffer RXB has stored the reception data signal from the MBat the frequency CF, it outputs the stored reception data signal to the terminal TPO at the frequency CF

Integrated test circuit, a test circuit, and a test method for performing transmission and reception processing to and from a first and a second macro block at a first frequency

A test circuit comprises a selector SELhaving a first input to which signals MOUT from a macro block MBare input and a second input to which test input signals TINand TINfor a macro block MBare input, and a selector SELhaving a first input to which a signal SQ from the SELis input and a second input to which a signal MOUT from the MBis input. In a first test mode in which the MBis tested, the SELoutputs the signals MOUT from the MBto a first input of the SEL, and the SELoutputs the signal SQ from the SELto the MB. In a second test mode in which the MBis tested, the SELoutputs the test input signals TINand TINfor the MBto the MB, and the SELoutputs the signals MOUT from the MBas a test output signal TOUT for the MB

Test circuit, integrated circuit, and test method

A transmitter circuit including: a current driver which current-drives differential signal lines; and a voltage driver which is electrically disconnected from at least one of the differential signal lines in a normal transfer mode, and is electrically connected to the at least one of the differential signal lines and voltage-drives the at least one of the differential signal lines in a power-down mode. The voltage driver outputs a power-down voltage for setting a receiver circuit to the power-down mode or a wakeup voltage for canceling the power-down mode of the receiver circuit, to the at least one of the differential signal lines. The current driver transmits a power-down command to the receiver circuit by current-driving the differential signal lines in the normal transfer mode.

Transmitter circuit, receiver circuit, interface circuit, and electronic instrument

A data transfer control device including a buffer is provided which includes an EParea (a data storage area set to FIFO) and a CSW area (a randomly accessible status storage area), when data and a CSW are allocated as information to be transferred through one end point EPWhen a phase has switched from a USE data phase (data transport) to a status phase (status transport), the information read area is switched from the EParea to the CSW area. and IN data to be transferred from the end point EPto a host is read from the CSW area. A CSWarea for success status and a CSWarea for non-success status are provided, and a status block packet in which is set either success or non-success default information is previously written therein.

A buffer is provided with a CBW area (a randomly accessible command storage area) and an EParea (data storage area set to FIFO), when a CBW and data are allocated as informations to be transferred through one end point EP. When a phase switches from a USB command phase (command transport) to a data phase (data transport), the information write area is switched from the CBW area to the EParea and OUT data transferred from the host to the end point EPis written into the EParea. The area switches from the CBW area to the EParea on condition that an acknowledgment has returned to the host in the command phase. In case of a toggle missing, area switching does not occur even if ACK is returned.

Growing community of inventors

Sapporo, Japan

Takuya Ishida