Toshiba Memory Corporation

Kioxia Corporation

Kabushiki Kaisha Toshiba

Takuya Inatsuka

Megumi Ishiduki

Tadashi Iguchi

Murato Kawai

Hisashi Kato

Osamu Matsuura

Taichi Iwasaki

Yoichi Minemura

Yoshihiro Yanai

Hideki Inokuma

Hajime Kaneko

Takuya Mizutani

Kazuhide Takamura

A semiconductor device includes a substrate including an element region that includes a first extending portion extending in a first direction and a plurality of first protruding portions protruding from the first extending portion in a second direction intersecting the first direction. The device further includes a first plug provided on the first extending portion and extending in the first direction and in a third direction intersecting the first direction and the second direction. The device further includes a plurality of gate electrodes respectively provided above the plurality of first protruding portions so as to respectively overlap with the plurality of first protruding portions in the third direction.

Semiconductor device

According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.

Semiconductor memory device

A semiconductor device according to an embodiment includes an N-well region, a first gate electrode, a single-crystal first semiconductor, and a first contact. The N-well region includes two P-type impurity diffusion regions. The first gate electrode is provided above the N-well region between the two P-type impurity diffusion regions. The first gate electrode is opposed to the N-well region via a gate insulating film. The single-crystal first semiconductor is provided in a columnar shape on the P-type impurity diffusion region. The first contact includes a polycrystalline second semiconductor. The second semiconductor is provided on the first semiconductor and includes P-type impurities.

According to one embodiment, a semiconductor device includes: a stack body including an insulator, a first conductor and a second conductor stacked stepwise by interposing the insulator and electrically disconnected from each other; and a first contact plug which reaches the first conductor from a region above the stack body. The first conductor includes a first portion positioned below the insulator, a second portion positioned above the insulator, and a third portion that electrically connects the first portion of the first conductor and the second portion of the first conductor. The third portion of the first conductor is provided in an opening formed on the insulator.

Semiconductor device and manufacturing method of semiconductor device

A semiconductor device according to an embodiment includes an N-well region, a first gate electrode, a columnar epitaxial layer, and a first contact. The N-well region includes two P-type impurity diffusion regions. The first gate electrode is provided above the N-well region between the two P-type impurity diffusion regions. The first gate electrode are opposed to the N-well region via a gate insulating film. The columnar epitaxial layer is provided on the P-type impurity diffusion region. The epitaxial layer includes a first semiconductor layer including P-type impurities. The first contact is provided on the first semiconductor layer of the epitaxial layer.

A semiconductor memory device includes a first member spreading along a first direction and a second direction, a stacked body provided on a third-direction side when viewed from the first member, and a second member provided inside the first member and exposed at a surface of the first member on the third-direction side. A configuration of an end portion in the first direction of the stacked body is a staircase configuration having terraces formed every conductive film. The second member is made from a material different from a material of the first member. The second member is totally disposed in a region opposing a total length of an end edge of the stacked body on the first-direction side, and not disposed in an outer region of the stacked body on the second-direction side.

A semiconductor storage device includes a substrate, a stack of first insulating layers and conductive layers that are alternately formed on the substrate in a memory region and a peripheral region and electrically insulated from each other, a second insulating layer covering the stack of the first insulating layers and the conductive layers in the peripheral region, and a plurality of contact wirings formed in the peripheral region, each contact wiring extending from an upper surface of the second insulating layer towards the substrate and electrically connected to a corresponding one of the conductive layers. In the peripheral region, each conductive layer has an extended portion that covers side and upper surfaces of an end portion of a first insulating layer that is formed immediately thereabove, and each contact wiring is in direct contact with the extended portion of the corresponding conductive layer.

Semiconductor memory device having a stepped structure and contact wirings formed thereon

A semiconductor memory device includes a substrate having a memory region and a peripheral region that are adjacent to each other, and a plurality of insulating layers and a plurality of wiring layers that are alternately formed on the memory region and the peripheral region of the substrate. On the memory region, the insulating layers and the wiring layers are alternately formed along a thickness direction of the memory device. On the peripheral region, first portions of the insulating layers and first portions of the wiring layers are alternately formed along the thickness direction and second portions of the insulating layers and second portions of the wiring layers are alternately formed along a lateral direction. A width of the second portion of each of the wiring layers in the lateral direction is greater than a thickness of the first portion of the wiring layer.

Semiconductor memory device and method of manufacturing semiconductor memory device

A semiconductor memory device includes a substrate, a plurality of insulating layers and wiring layers that are alternately formed, and a plurality of first layers and second layers that are alternately formed. The substrate has a memory region extending in first and second directions along a surface of the substrate, a step region adjacent to the memory region in the first direction, and a peripheral region adjacent to the memory region and the step region in the second direction. The insulating layers and the wiring layers are formed on the memory region and the step region. The first and second layers are formed on the peripheral region. Each of the first layers is formed on a same level as and in contact with one of the insulating layers, and each of the second layers is formed on a same level as and in contact with one of the wiring layers.

Semiconductor memory device having memory cells arranged three-dimensionally and method of manufacturing the same

A nonvolatile semiconductor memory device comprises: a memory cell region having a memory cell disposed therein; a peripheral region including a first stepped structure in which an end of a lower first layer is further from the memory cell region than is an end of an upper first layer; and a second stepped structure disposed on the first stepped structure, in which an end of a lower third layer is disposed further from the memory cell region than is an end of an upper third layer, a length in a second direction being shorter than a length in the second direction of the first layer or the second layer contacted by the second stepped structure, and a length in a third direction of the second stepped structure being shorter than a length in the third direction of the first layer or the second layer contacted by the second stepped structure.

Growing community of inventors

Yokkaichi, Japan

Takuya Inatsuka