Nec Electronics Corporation

Nec Corporation

Sanyo Electric Co., Ltd.

Takuya Hirota

Satoshi Yamamoto

Atsushi Nakagawa

Takao Yanagida

Hideo Inaba

Masahiro Yoshida

Takato Shimoyama

Noriaki Komatsu

Kayoko Ikegami

Susumu Takano

Hisashi Kameyama

Yusuke Omote

Yoshiyuki Katou

Jeewook Chang

Motoji Takeuchi

Mitsuhiro Hamada

Yuuji Torige

A power supply device includes a spike absorption circuit that suppresses an avalanche breakage of a current shutdown switch due to a kickback voltage that may appear in response to the cut-off of a load current. The current shutdown switch is connected to secondary batteries. The spike absorption circuit is a series circuit of a protection switch, formed of a semiconductor element, and a diode. The power supply device further includes: a small-signal switch that controls turn-on and turn-off of the protection switch; and a delay circuit that maintains the small-signal switch in an ON state over a setup time after a current shutdown timing of the current shutdown switch. The delay circuit maintains the small-signal switch in the ON state over the setup time (T), and the small-signal switch thereby causes the protection switch to the ON state. Then, the spike absorption circuit damps the kickback voltage.

Power supply device

A semiconductor device (DRAM) according to one embodiment of the present invention includes a plurality of pairs of digit lines (digit True, Not) connected to a memory cell, a common signal line pair (main I/O True, Not) connected to the plurality of pairs of digit lines in common, a main I/O equalizer performing precharge of the common signal line pair, and a control circuit determining whether the precharge operation is continued irrespective of a signal level of a mask signal input from an outside.

Semiconductor device and method of controlling the same

In a conventional equalizer circuit, in an equalizing operation for setting voltages of a wiring pair having a predetermined voltage difference therebetween to be the same, it takes a long time to make the voltages of the wirings in a pair converge to a voltage having an offset with respect to a midpoint voltage of the voltages of the wiring pair after the equalizing operation. According to an equalizer circuit of the present invention, provided is an equalizer circuit () which sets the voltages of a first wiring (SAP) and a second wiring (SAN) to be substantially the same and which has a first transistor (N) connected between the first wiring (SAP) and a first power supply circuit (for example, HVDD&#x2212;Va) and a second transistor (N) connected between the first wiring SAP and the second wiring (SAN). The equalizer circuitmakes the first transistor (N) conductive, and then makes the second transistor (N) conductive.

Equalizer circuit and method of controlling the same

A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.

Semiconductor memory with a delay circuit

A semiconductor storage device has first and second cell arrays including a plurality of memory cells to store data, a sense amplifier selectively connected with either one of the first and second cell arrays, a first precharge circuit to set a pair of bit lines in the first cell array to a predetermined voltage, a second precharge circuit to set a pair of bit lines in the second cell array to a predetermined voltage, a first switch circuit to connect the sense amplifier with the first cell array, a second switch circuit to connect the sense amplifier with the second cell array, and a switch controller to control conductive state of the first and second switch circuits. In non-selection state where the sense amplifier does not access any of the cell arrays, the switch controller controls one of the switch circuits into conducting state.

Semiconductor storage device

Semiconductor memory device and semiconductor memory device control method

Semiconductor memory device and semiconductor device and semiconductor memory device control method

A semiconductor storage device according to an embodiment of the present invention includes: a plurality of word lines; a plurality of memory cells corresponding to the plurality of word lines; and a refresh circuit for sequentially driving the plurality of word lines to refresh each of the plurality of memory cells based on a timer period, which sets the timer period in accordance with a disturb amount in an active mode upon shift from the active mode to the standby mode.

Semiconductor storage device and operating method therefor

Disclosed is a semiconductor storage device in which control is performed in such a manner that if the refresh operation is not being performed when a chip-select signal undergoes a transition from an inactive (standby) state to an active state, read or write access is executed immediately and if the refresh operation is in progress when the chip-select signal undergoes a transition from the inactive state to the active state, a wait signal for causing read or write access to wait is generated by a wait generating circuit.

A semiconductor memory device has common terminals shared between a part or all of address terminals for receiving n bits of an address signal and data terminals for outputting a data signal with its bit width of n bits or less and dedicated address terminals for receiving m bits of the address signal, wherein at the time of a read, after the n bits of the address signal have been input, a plurality of data signals within a selected page are consecutively read out through the common terminals using the m bits of the address signal input from the dedicated address terminals.

Semiconductor memory device and control method thereof

A semiconductor memory device adapted for avoiding collision between the selection period of a word line for a refresh and the selection period of a word line for a read/write, comprises a cell array including a plurality of memory cells that require refreshing for retention of storage data and means for exercising control so that when a read/write request is input in a clock cycle following a clock cycle for performing a refresh operation, a read/write operation in the cell array is delayed by at least one clock cycle, and the read/write operation is started after completion of the refresh.

Semiconductor memory device

Refresh of memory cells is performed periodically by a refresh timer, and collision between memory access and memory refresh is avoided. When memory access occurs, an F/Fis set by a one shot pulse from an OS circuit, a memory access request is inputted to a memory accessing pulse generator circuitthrough a NOR gate, and a latch control signal LC and an enable signal REN are outputted. When a refresh request from the refresh timer is inputted to an AND gateduring the memory access, the output of the NOR gateis at the 'L' level, and the refresh request is blocked by the AND gate. Thereafter, at the time when the latch control signal LC is turned into the 'L' level, F/Fsandare reset, the output of the NOR gateis turned into the &#x201c;H&#x201d; level, the refresh request is inputted to a refreshing pulse generator circuit, and a refresh enable signal RERF is outputted.

Semiconductor storage device and refresh control method thereof

A semiconductor memory device capable of a further reduction in power consumption for refresh operation is provided. Cell arrays S, Sare divided into respective four blocks B&#x2dc;Band B&#x2dc;B. In a normal read/write operation, by address data designating a word line, one of the cell arrays is selected, and also one block is selected in the selected cell array, and further one word line is selected in the selected block. In a refresh operation, one of the cell arrays is selected, and four blocks in the selected cell array are simultaneously refreshed. Namely, respective one word line is selected from each of the four blocks, and the selected word lines are refreshed, thereby to reduce a power comsumption as compared to when the plural cell arrays are refreshed.

Semiconductor storage and its refreshing method

A semiconductor memory device, capable of being accessed at a high speed, according to the present invention, is provided, and is configured with the changeover point in time between the pre-charge operation and a word line selection operation on the far-end side of the sense amplifier being earlier than that on the near-end side of it. There are provided word selection signal input buffer, block selection signal input buffer, digit selection signal input buffer on semiconductor chip, decoders, which decode the said signals, drivers for the output signal of each decoder, memory block, which is stored with information, and gate circuit, which selects a column of memory cells in a memory block. Drivers for the word selection signal and block selection signal are laid out in the middle of chip and near far-end side pre-charge unit, which is located the farthest from the sense amplifier (which is deployed in near-end side pre-charge unit.

Semiconductor memory device improving data read-out access

A semiconductor chip has a first ground line for maintaining a stable ground potential for the internal circuit. The first ground line is connected to a second ground line disposed on a scribe region of the semiconductor chip via a bonding pad, which is connected to an external lead frame. I/O circuit has a third ground line directly connected to the second ground line without passing the bonding pad. The noise propagated from the third ground line to the first ground line is reduced by passing the noise through the bonding pad.

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Kanagawa, Japan

Takuya Hirota