Denso Corporation

Nippondenso Co., Ltd.

Takuya Harada

Masakiyo Horie

Takuya Honda

Hirofumi Isomura

Akimasa Niwa

Takayuki Aono

Kenji Ito

Nobuyuki Tanaka

Shuji Agatsuma

Hiroyuki Takeuchi

Kazuhiro Nagai

Tetsuyasu Kitamura

Yoshinori Fujihashi

Koji Oshita

A ring oscillator is configured with a multiple number of logic inverting circuits in a ring shape and generates multi-phase clock signals. A period measuring unit measures a period of a reference clock inputted thereto by the multi-phase clock signals of the ring oscillator and outputs a measured period as a period data value. A frequency spreading calculation unit calculates a frequency spreading command value in accordance with a frequency spreading rate, a frequency spreading period and the period data value of the period measuring unit, which are inputted. A pulse generation unit generates a clock pulse corresponding to the frequency spreading command value in accordance with a data value determined by addition of the frequency spreading command value to the period data value.

Frequency spreading circuit

An input signal processing device includes an oscillator circuit, a signal processing circuit, and a control circuit. The oscillator circuit performs an oscillation operation to output a clock signal. The signal processing circuit operates based on the clock signal outputted from the oscillator circuit. The signal processing circuit performs a predetermined process to an input signal when a level of the input signal changes and outputs a signal after the predetermined process. The control circuit instructs the oscillator circuit to start the oscillation operation based on a level change of the input signal. The control circuit instructs the oscillator circuit to stop the oscillation operation when the signal processing circuit finishes the predetermined process.

Input signal processing device

An output data correction device is provided for an A/D conversion circuit that achieves high precision over input voltage domains. An estimated maximum input ranging from 0 V to 5 V is divided into domains. A comparison circuit decides to which of the domains a voltage Vin input to a pulse phase-difference encoding circuit belongs. Control logic and a digital analog controller (DAC) select and transmit reference voltages associated with each of the domains. When each of the reference voltages is selected, a quadratic functional equation is computed and determined. A graph of the function passes coordinate points representing the reference voltages in a coordinate system with reference voltages and A/D-converted data values as dimensions. When each input voltage is selected, the A/D-converted digital data is corrected using the quadratic functional equation associated with the domain to which the input voltage Vin is decided to belong.

Output data correction device for analog-to-digital conversion circuit and analog-to-digital converted output data correction method

In an A/D conversion device, one level shift circuit shifts an input voltage to the low potential side by Vt, and another level shift circuit shifts the input voltage to the high potential side by Vt. A multiplexer selects either of the shifted voltages to an A/D converter. In a correction mode, a correction data holding circuit holds values of reference voltages that are also A/D converted after being passed through the one level shift circuit and values of reference voltages that are A/D converted by being passed through the other level shift circuit, as correction values. A correction control circuit corrects the A/D converted value using the correction values.

A/D conversion device having input level shift and output correction function

The A/D converter has first and second PPDC circuits (pulse-phase-difference coding circuits). The first PPDC circuit performs A/D conversions on the reference voltage and on the voltage signal amplified by an amplifier in an alternating sequence, the amplifier using the reference voltage as a potential base thereof. The second PPDC circuit performs A/D conversions always on the reference voltage. The A/D-converted data set of the voltage signal outputted from the first PPDC circuit is corrected depending on the difference between the A/D-converted data set of the reference voltage outputted from the second PPDC circuit when the first PPDC circuit A/D-converts the reference voltage and the A/D-converted data set of the reference voltage outputted from the second PPDC circuit when the first PPDC circuit A/D-converts the voltage signal.

Analog-to-digital converter and method of analog-to-digital conversion

A rotation position detecting device includes an angular signal generator which generates pulses the cycle period of which is even or equal when a rotating object rotates at a constant rotation speed and a non-pulse portion which corresponds to a reference position, an up-down command circuit for generating an up-down command signal the frequency of which is divided to a half of the frequency of the angular signal, a pair of first counters for counting up or down the clock signal when the up-down command signal changes from a first level to a second level to reset and subsequently counting down the clock signal when the up-down command signal changes from the second level to the first level, a pair of processing circuits for providing a first and second reference values, a pair of counters which generates detection signals when the counted number of the counters becomes smaller than the first or the second reference value.

Rotation position detecting device

A semiconductor integrated circuit device is provided to reduce the adverse effect of PWM noise occurring in a PWM driving section on an analog voltage processing section in an IC, in which digital and analog circuits are combined on a single chip. A sampling signal generation circuit outputs a sampling signal St to an A/D converter at a predetermined time when 'delay time td+allowance time ta' has elapsed from a start signal Sp. The delay time td is shorter than 'the minimum time width of H level of PWM signal SPWM&#x2212;allowance time ta'. The delay time td is also time from the variation of level of the PWM signal SPWMto actual variation in the passage of current through a power section.

Semiconductor integrated circuit device having a sampling signal generation circuit

A memory control apparatus for controlling the operation of a memory array in a serial memory employs a command control section for registering the bits of an instruction which is received as an externally supplied set of serial data in conjunction with a corresponding series of cycles of a clock signal, with each set of serial data formatted as a command data portion preceded by a start bit, whereby the shifting of the start bit into the MSB stage of the shift register is detected and used to terminate supplying the clock signal to the shift register, thereby eliminating the use of a counter circuit. Any additional clock signal cycle following shifting of the start bit into the MSB stage of the shift register is detected, so that operating errors caused by noise in the received clock signal can be reliably eliminated.

Memory control apparatus for serial memory

In a memory controller, a serial data including an instruction bit train with addition of a start bit, a clock signal, a chip enable signal, and a reset signal are inputted. During the active period in which the chip enable signal is being inputted, the serial data is stored depending on the clock signal and an enabling signal is generated based on the end timing of active period. Thereby, memory access is executed depending on contents of the instruction bit train. However, when the relevant apparatus is reset during the active period, generation of the enabling signal based on the end timing of the active period is inhibited.

Memory controller and serial memory

A direct-current power supply circuit, incorporated in an IC card, includes a coil for receiving an amplitude-modulated signal from an external device through electromagnetic induction. A full-wave rectifying circuit rectifies the amplitude-modulated signal received by the coil. The rectified output signal is used to charge a smoothing capacitor. A clamp circuit controls the terminal voltage of the smoothing capacitor to a predetermined level so as to produce a power supply voltage. The clamp circuit controls an output transistor to stabilize the power supply voltage to a constant level. Furthermore, the direct-current power supply circuit includes a short-circuit preventing circuit to forcibly turn off the output transistor when the electric potential difference between both ends of the coil is smaller than a predetermined value, thereby preventing the power supply voltage from suddenly decreasing due to delay of operation of the circuit elements when the coil output becomes zero due to amplitude modulation.

Direct-current power supply circuit having control sections with at least one control section having priority over another control section

A buffer circuit includes a signal input terminal and a signal output terminal. A first operational amplifier includes a differential amplifier circuit having an input transistor of an N-channel MOS type. The first operational amplifier has an inverting input terminal and an output terminal connected to each other. The first operational amplifier has a non-inverting input terminal connected to the signal input terminal. A second operational amplifier includes a differential amplifier circuit having an input transistor of a P-channel MOS type. The second operational amplifier has an inverting input terminal and an output terminal connected to each other. The second operational amplifier has a non-inverting input terminal connected to the signal input terminal. A first switching device operates for connecting the output terminal of the first operational amplifier to the signal output terminal when a voltage of an input signal applied to the signal input terminal is in a range where the first operational amplifier is operative. A second switching device operates for connecting the output terminal of the second operational amplifier to the signal output terminal when the voltage of the input signal applied to the signal input terminal is in a range where the second operational amplifier is operative.

Buffer circuit

An offset voltage correction circuit for an operational amplifier (1) includes an offset voltage varying device (16, 17, 20, 21-23) for varying an offset voltage in the operational amplifier (1) in response to an offset voltage control value. A comparing device (25) operates for comparing an output voltage from the operational amplifier (1) with a prescribed reference voltage. A control device (19, 300) operates for outputting the offset voltage control value to the offset voltage varying device, for changing the offset voltage control value, for storing, in response to a result of the comparing by the comparing device (25), a digital signal representative of the offset voltage control value at which the output voltage from the operational amplifier (1) and the prescribed reference voltage are equal, and for correcting the offset voltage in the operational amplifier (1) in response to the stored digital signal.

Offset voltage correction circuit

A waveform shaping apparatus includes a comparing device for comparing a sensor output signal with a threshold voltage to convert the sensor output signal into a waveform shaped signal. The comparing device outputs the waveform shaped signal. The waveform shaping apparatus also includes a frequency-to-voltage converting device for generating the threshold voltage in response to a frequency of the output signal from the comparing device. In the frequency-to-voltage converting device, a clock signal is generated in response to the output signal from the comparing device. The clock signal has a period proportional to a period of the output signal from the comparing device. A counting device is operative for counting pulses in the clock signal generated by the clock signal generating device for every given period, and outputting a signal representing a counted pulse number depending on the frequency of the output signal from the comparing device. A D/A converting device is operative for converting the output signal from the counting device into a voltage signal which depends on the counted pulse number. The threshold voltage is generated in response to the voltage signal generated by the D/A converting device.

Valuable threshold waveform shaping apparatus

An input voltage Va and a threshold voltage Vc are compared in a comparator 21 to shaping the waveform of a sensor signal. The period of the output signal of comparator 21 is measured by a period measuring circuit 4. A stepped waveform voltage generating circuit 5 generates a stepped waveform voltage based on the measured period. The stepped waveform voltage is converted into corresponding current in a V-I conversion circuit 6. The current of V-I conversion circuit 6 is supplied to a resistance 23d or 23e via an analog switch 22a or 22b which turns on or off in response to the operation of comparator 21, thereby applying a stepped offset voltage to input voltage Va threshold voltage Vc to perform the hysteresis operation.

Waveform shaping apparatus

In a frequency-to-voltage converting circuit, a clamping frequency is maintained constant without being adversely influenced by circuit constants, and temperature characteristics. The frequency-to-voltage converting apparatus has voltage converting means for converting a frequency of an input pulse signal into a voltage, arranged by frequency judging means for judging whether or not the frequency of the input pulse signal reaches a predetermined clamping frequency. Setting pulse signal generating means outputs a setting pulse signal having the clamping frequency, and means for causing the voltage converting means to convert the frequency of the input pulse signal into the voltage when the frequency of the input pulse signal does not reach the clamping frequency based on a judgement result of the frequency judging means. The voltage converting means is caused to convert the clamping frequency of the setting pulse signal derived from the setting pulse signal generating means when the frequency of the input pulse signal reaches the clamping frequency.

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Kariya, Japan

Takuya Harada