Toshiba Memory Corporation

Kioxia Corporation

Takuya Haga

Konosuke Watanabe

Kenji Funaoka

Toru Katagiri

Taro Iwashiro

Shuichi Watanabe

A memory system, which is connectable to a host, includes a non-volatile memory and a controller configured to store data in the non-volatile memory and in a memory region within the host and read the data from the memory region within the host. The controller includes a first encoding/decoding circuit configured to execute encoding/decoding with a first encoding scheme, a second encoding/decoding circuit configured to execute encoding/decoding with a second encoding scheme having a higher error correcting capability than an error correcting capability of the first encoding scheme, an encoding scheme selecting circuit configured to select an encoding/decoding circuit from the first encoding/decoding circuit and the second encoding/decoding circuit to perform encoding of data to be stored in the memory region, based on information about the data read from the memory region.

Memory system

A memory system includes a nonvolatile semiconductor memory, and a controller configured to maintain a plurality of log likelihood ratio (LLR) tables for correcting data read from the nonvolatile semiconductor memory, determine an order in which the LLR tables are referred to, based on a physical location of a target unit storage region of a read operation, and carry out correcting of data read from the target unit storage region, using one of the LLR tables selected according to the determined order.

Memory system that carries out soft bit decoding

A memory system includes a semiconductor storage device and a memory controller. The memory controller includes a command buffer and a descriptor buffer. The memory controller stores a first command received from outside in the command buffer, fetches a first descriptor from the host device, based on the stored first command, stores the fetched first descriptor in the descriptor buffer, stores a second command received from the outside in the command buffer, discards an unused part of the first descriptor from the descriptor buffer, fetches a second descriptor from the host device, based on the stored second command, and stores the fetched second descriptor at an address where the discarded part of the first descriptor was stored.

According to one embodiment, there is provided a memory system including a nonvolatile semiconductor memory, a bus, and a controller. The nonvolatile semiconductor memory includes a first chip and a second chip. The bus is connected to the first chip and the second chip in common. The controller issues a first command to the first chip via the bus. The controller queues a second command whose access destination is identified to be the first chip at a first timing while the first chip is executing the first command. The controller issues to the second chip a third command whose access destination is identified to be the second chip after the first timing, via the bus in priority over the second command, while the first chip is executing the first command or after the execution of the first command finishes.

Memory system including a plurality of chips and a selectively-connecting bus

A memory system includes a nonvolatile semiconductor memory and a controller. The controller is configured to maintain a plurality of log likelihood ratio (LLR) tables for predicting a value of data read from the nonvolatile semiconductor memory, count a number of times that each of write operations, erase operations, and read operations have been carried out with respect to each unit storage region of the nonvolatile semiconductor memory, determine an order in which the LLR tables are referred to, based on the counted number of the read operations and one of the counted number of the write operations and the counted number of the erase operations, which correspond to a target unit storage region of a read operation, and carry out decoding of data read from the target unit storage region of the read operation, using one of the LLR tables selected according to the determined order.

According to one embodiment, a memory controller controlling write to and read from a 3D NAND flash memory including a plurality of blocks, one block being constituted by a plurality of pages stacked in a depth direction includes a frame generator that generates frame data including an error detecting code or an error correcting code, and a frame divider that divides the frame data to generate a plurality of divided frames including a first divided frame and a second divided frame. The first divided frame and the second divided frame are written into different pages from one another.

Growing community of inventors

Yokohama Kanagawa, Japan

Takuya Haga