Hitachi, Ltd.

Other

Hitachi Engineering Services Co., Ltd.

Hiatchi, Ltd.

Hitachi Service Engineering Co., Ltd.

Hitachi Engineering Service

Hitachi Engineering & Services, Inc.

Service Engineering Co. Ltd.

Takuya Fukuda

Masayoshi Saito

Yoshitaka Nakamura

Michio Ohue

Nobuyoshi Kobayashi

Kazuo Suzuki

Masayoshi Hirasawa

Tadasi Sonobe

Satoru Yamada

Isamu Asano

Tsuyoshi Tamaru

Yoshitaka Tadaki

Toshihiro Sekiguchi

Keizo Kawakita

Katsuaki Saito

Hideo Aoki

Masayuki Suzuki

Yoshifumi Kawamoto

Shinichi Fukada

Yuzuru Ohji

Naohiro Momma

Shigeru Takahashi

Naoki Fukuda

Hidekazu Goto

Hiroyuki Uchiyama

Katsuhiko Hotta

Masayuki Kojima

Yasuhiro Mochizuki

Hiroyuki Maruyama

Junji Sato

Fumiyuki Kanai

Noboru Suzuki

Yukinobu Miyamoto

JaiHo Choi

Takao Watanabe

Norio Hasegawa

Toshiya Satoh

Shinpei Iijima

Atsuyoshi Koike

Yoshitaka Sugawara

Yutaka Misawa

Hideharu Yahata

Seikichi Tanno

Susumu Murakami

Yoshiteru Shimizu

Yasuhiro Sugawara

Ryouichi Furukawa

Misuzu Kanai

Satoru Todoroki

Kiyoshi Chiba

Shunichi Hirose

Atsushi Tsuchiya

Kiyosi Chiba

An SOG film obtained by heat-treating a polysilazan type SOG film at high temperature of about 800&deg; C. is used as a planarized insulating film to be formed on the gate electrode ( ; see FIGS. and ) of a MISFET (Qs, Qn, Qp) A polysilazan SOG film ( ) not subjected to such a heat treatment is used as interlayer insulating film arranged among upper wiring layers ( ).

Method of manufacturing semiconductor integrated circuit device having insulating film formed from liquid substance containing polymer of silicon, oxygen, and hydrogen

The new structure of a memory cell which enables avoiding the problem of a step without increasing the number of processes, the structure of a semiconductor integrated circuit in which a common part of the same substrate in a manufacturing process is increased and the structure of the semiconductor integrated circuit which allows measures for environment obstacles without increasing the number of processes are disclosed. Memory cell structure in which a capacitor is formed in the uppermost layer of plural metal wiring layers by connecting the storage node of the capacitor to a diffusion layer via plugs and pads is adopted. It is desirable that a dielectric film formed in a metal wiring layer under the uppermost layer and a supplementary capacitor composed of a storage node and a plate electrode are connected to the capacitor. It is also desirable that the plate electrode of the capacitor covers the chip.

Dynamic random access memory including a logic circuit and an improved storage capacitor arrangement

In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta O (tantalum oxide) film , the portions of bit lines BL and first-layer interconnect lines to of a peripheral circuit which are in contact with at least an underlying silicon oxide film are formed of a W film, the bit lines BL and the interconnect lines to being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines to and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.

Method of manufacturing a semiconductor integrated circuit device having a capacitor

Capacitors are stretched over a plurality of memory cells in the direction of a bit line in order to effectively utilize spaces between adjacent cells. In addition, by creating a cubic structure of each capacitor by adoption of a self-matching technique, the structure can be utilized more effectively. As a result, it is possible to assure a sufficient capacitor capacitance in spite of a limitation imposed by the fabrication technology and obtain an assurance of sufficient space between cells in a shrunk area of a memory cell accompanying high-scale integration and miniaturization of a semiconductor device.

Semiconductor device comprising capacitor cells, bit lines, word lines, and MOS transistors in a memory cell area over a semiconductor substrate

An SOG film obtained by heat-treating a polysilazan type SOG film at high temperature of about 800&deg; C. is used as a planarized insulating film to be formed on the gate electrode of a MISFET (Qs, Qn, Qp). A polysilazan SOG film not subjected to such a heat treatment is used as interlayer insulating film arranged among upper wiring layers ( ).

Method of manufacturing semiconductor integrated circuit device having insulatro film formed from liquid containing polymer of silicon, oxygen, and hydrogen

Semiconductor integrated circuit device and process for manufacturing the same

Semiconductor integrated circuit device and process for manufacture the same

A steplike offset between a memory cell array region and a peripheral circuit region, which is caused by a capacitor C, is reduced by an insulating film having a thickness substantially equal to the height of the capacitor C. Wiring or interconnection grooves are defined in the neighborhood of the surface of an insulating film whose surface is flattened by a CMP method. Further, connecting holes are defined in lower portions of the bottom faces of the interconnection grooves respectively. Second layer interconnections containing copper are formed within the interconnection grooves, and connecting portions containing copper are formed within the connecting holes. The second layer interconnections and first layer interconnections are connected to each other by the connecting portions whose lengths are shortened. The second layer interconnections and the connecting portions are integrally formed by a damascene method using the CMP method.

Semiconductor integrated circuit device

In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta O (tantalum oxide) film the portions of bit lines BL and first-layer interconnect lines to of a peripheral circuit which are in contact with at least an underlying silicon oxide film are formed of a W film, the bit lines BL and the interconnect lines to being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines to and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.

Method of manufacturing semiconductor integrated circuit device having a capacitor

A method of fabricating a semiconductor device having, for example, a memory cell array portion and a peripheral circuit portion is disclosed. By such a method, a first interlayer insulating film is formed on a semiconductor substrate, a first connection hole is formed by selectively removing a predetermined portion of the first interlayer insulating film, the sides of the first hole being substantially vertical to the bottom thereof, a first plug is formed by padding the first hole with a metallic film and, subsequently, a second interlayer insulating film is formed on the first insulating film, a second hole is formed by selectively removing a predetermined portion of the second interlayer insulating film, the sides of the second hole being substantially vertical to the bottom thereof, and a second plug aligned to be in direct connection with the first plug is formed by padding the second hole with the metallic film. A MOS transistor is formed on the semiconductor substrate before the first interlayer insulating film is formed and the first hole formed is extended to expose the diffused layer of the MOS transistor. The surfaces of both the first and second interlayer insulating films are smoothed by a chemical mechanical polishing (CMP) method. The process of padding the connection holes with the metallic film is effected through a CVD or selective CVD method.

Semiconductor integrated circuit device and method for fabricating the same

The present invention relates to a semiconductor device that includes a dynamic memory and logic circuits that are integrated on a single chip and that can avoid noise problems and signal delay. The portion above the memory is shielded with a shielding conductor that is biased to an equipotential. Wirings between logical blocks and bonding pads or between logical blocks are passed over the conductive layer. Wiring for logic circuits can be done in the same metal wiring layer in which the shielding conductor is provided. The shielding conductor can have a mesh-like structure to improve its integrity and wirings can be passed over conductive portions of the shielding layer to be protected from noise. In addition to the dynamic memory, other memories and analog circuits can be used instead of or in combination with the dynamic memory.

Semiconductor device having a shielding conductor

In order to improve connection reliability of a feeding interconnection connected to an electrode of each of the information storage capacitive elements of a DRAM, the formation of a through hole for connecting the information storage capacitive element formed over each memory cell selection MISFET and a feeding interconnection is performed in a process different from that for the formation of a through hole for connecting an interconnection of a second wiring layer in a peripheral circuit, which is formed over the information storage capacitive element and an interconnection corresponding to a first wiring layer.

Semiconductor integrated circuit device and method of manufacturing the same

Semiconductor integrated circuit device and method of manufacturing same

In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta,O,(tantalum oxide) film,the portions of bit lines BL and first-layer interconnect lines,to,of a peripheral circuit which are in contact with at least an underlying silicon oxide film,are formed of a W film, the bit lines BL and the interconnect lines,to,being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines,to,and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.

Semiconductor integrated circuit device, and method of manufacturing the same

A semiconductor integrated circuit device of the invention is provided with a memory cell array portion and a peripheral circuit portions. In the memory cell array portion, a plurality of plugs which penetrate each of a plurality of interlayer insulating films and the sides of which are almost vertical are directly connected in sequence. In the peripheral circuit portion, a plurality of plugs are mutually connected through contact pads for wiring.

Semiconductor integrated circuit device having multi-level wiring

Growing community of inventors

Kodaira, Japan

Takuya Fukuda