Sandisk Technologies Inc.

Samsung Electronics Co., Ltd.

Takuya Ariki

Toru Miwa

Naoki Ookuma

Hiroyuki Ogawa

Hiroki Yabe

Koichiro Hayashi

Fumiaki Toyama

Masatoshi Nishikawa

Hardwell Chibvongodze

Yuki Fujita

Masahito Takehara

Kazuki Yamauchi

Jongmin Park

Qui V Nguyen

Kazutaka Yoshizawa

Makoto Yoshida

Yuichiro Nakagaki

A non-volatile memory apparatus is provided and includes a substrate having a major surface extending longitudinally. A stack of first and second sets of word lines and insulating layers extends along and over the major surface longitudinally and alternating with and overlying one another vertically to define a device region. The first and second sets of word lines each respectively extends longitudinally beyond a first and second side of the device region a decreasing longitudinal distance from the device region as a vertical distance from the major surface increases to define first and second stepped contact regions. Word line contacts extend vertically in the first and second stepped contact regions. The second set of word lines in the first stepped contact region do not contact the word line contacts and the first set of word lines in the second stepped contact region do not contact the word line contacts.

Word line architecture for three dimensional NAND flash memory

A non-volatile memory device comprising a memory cell region having a plurality of co-planar memory cell planes arranged in a plane parallel to a semiconductor substrate, with each memory cell plane comprising a plurality of sub-planes disposed adjacent one another along an axis that is parallel to the substrate. Further, each memory cell plane comprises a plurality of sense amplifier regions arranged along the axis in an alternating pattern with the sub-planes such that adjacent to each sub-plane is a sense amplifier region and each sense amplifier region is operable with respect to at least a fraction of the bit lines of the two sub-planes immediately adjacent the sense amplifier region.

Memory plane structure for ultra-low read latency applications in non-volatile memories

The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.

Word line decoder circuitry under a three-dimensional memory array

A random access memory is provided including a plane structure comprising a plurality of sense amplifiers, each including a local data latch, a pair of local busses connected to each of the data latches, a differential data bus, and a pair of redrivers connected between the pair of local busses and the differential data bus.

Differential dbus scheme for low-latency random read for NAND memories

A memory device comprising a semiconductor substrate in which a memory cell region and a peripheral circuitry region are defined, wherein the memory cell region has a plurality of non-volatile memory cells arranged in one or more arrays and the peripheral circuitry region has at least one sense amplifier region comprised of at least one low voltage transistor. Further, a deep N-well region is formed in the substrate, wherein the memory cell region and the peripheral circuitry region are placed on the deep N-well region such that, in the event that a high erase voltage (VERA) is applied to the memory cell region during an erase operation, the high erase voltage is applied to all terminals of the at least one low voltage resistor, thereby protecting the low voltage transistor by preventing it from experiencing a large voltage difference between its terminals.

Area effective erase voltage isolation in NAND memory

A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.

Three-dimensional memory device containing bit line switches

Word line switches in a word line decoder circuitry for a three-dimensional memory device can be formed as vertical field effect transistors overlying contact via structures to the electrically conductive layers for word lines. Via cavities in a dielectric material portion overlying stepped surfaces of the electrically conductive layers can be filled with a conductive material and recessed to form contact via structures. After forming lower active regions in the recesses, gate electrodes can be formed and patterned to form openings in areas overlying the contact via structures. Gate dielectrics can be formed on the sidewalls of the openings, and transistor channels can be formed inside the openings of the gate electrodes. Upper active regions can be formed over the transistor channels.

Integration of word line switches with word line contact via structures

A level shifter circuit is presented that can apply a negative voltage level to non-selected blocks while still being able to drive a high positive level when selected. An exemplary embodiment presents a negative level shifter that is not susceptible to low voltage pfet breakdown. This allows for a high voltage level shifter (transfer gate) that can drive a negative level for unselected blocks and, when enabled for a selected block, can still drive a positive high voltage level. By using a pair of low voltage PMOS device whose n-wells share the same level as other PMOS transistors in the design, layout area can be minimized. The gates of this pair of PMOSs are connected to VSS, thereby preventing these low voltage PMOS devices from thin oxide breakdown.

Level shifter with negative voltage capability

A voltage regulator includes a voltage regulator unit configured to output a step voltage and a damping resistance switching unit coupled between a load and an output node of the voltage regulator and configured to select an optimal damping resistance value based on a required load capacity.

Flash memory and related voltage regulator

Provided is a discharge circuit. The discharge circuit for discharging two positive and negative high voltages after an erase operation of a non-volatile memory includes: a negative high voltage side discharge unit flowing constant current from a supply voltage to a negative high voltage node of the non-volatile memory to discharge the negative high voltage node; and a positive high voltage side discharge unit flowing constant current from a positive high voltage node of the non-volatile memory to a ground voltage to discharge the positive high voltage node, the positive high voltage side discharge unit simultaneously operating with the negative high voltage side discharge unit, wherein values of the constant currents flowing from the positive and negative high voltage side discharge units are approximately equal.

Discharge circuit

Provided are a write voltage generating circuit of a non-volatile memory cell and a write voltage generating method. The write voltage generating circuit includes a voltage generating unit providing a preliminary write voltage at a level below a defined target level, a voltage sensing unit receiving the preliminary write voltage and a reference signal, and in response to a comparison between the preliminary write voltage and the reference signal generating a start signal, and a switching unit generating and applying a write voltage derived from the preliminary write voltage at a writeable level to a non-volatile memory cell during the write operation in response to the start signal, wherein the writeable level is less than the target level.

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Yokohama, Japan

Takuya Ariki