Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Takuo Ohashi

Fumiki Aiso

Masaaki Higuchi

Katsuyuki Sekine

Tatsuya Okamoto

Takayuki Ito

Kiyotaka Miyano

Ryota Suzuki

Kouji Matsuo

Toshihiko Iinuma

Kunihiro Miyazaki

Tatsuo Izumi

Yusuke Oshiki

Takaharu Itani

Kazuharu Yamabe

Kenichi Yoshino

Masahiro Fukuda

Atsushi Fukumoto

Hajime Nagano

Shinji Miyazaki

Daisuke Nishida

Norihiko Kamiura

Motoki Fujii

Mari Kusunoki

A substrate treatment apparatus according to an embodiment of the present invention includes a chamber, a stage, a gas discharger, a plasma generator, and a rotation mechanism. The stage supports a semiconductor substrate in the chamber. The gas discharger discharges a film formation gas toward the semiconductor substrate from a position opposing the stage. The plasma generator is provided on the gas discharger and generates plasma in the chamber during discharge of the film formation gas. The rotation mechanism rotates the stage during generation of the plasma.

Substrate treatment apparatus and manufacturing method of a semiconductor device

A semiconductor memory device includes a conductive layer; a first electrode layer provided above the conductive layer; a second electrode layer provided between the conductive layer and the first electrode layer; a first semiconductor channel body extending through the first electrode layer in a first direction from the conductive layer to the first electrode layer; a second semiconductor channel body provided between the conductive layer and the first semiconductor channel body, the second semiconductor channel body extending through the second electrode layer; and an insulating layer provided between the second semiconductor channel body and the second electrode layer. The second semiconductor channel body includes a first recessed portion in a lateral surface facing the second electrode layer, and the second electrode layer includes a second recessed portion in a surface facing the second semiconductor channel body.

Semiconductor memory device and method for manufacturing same

According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are provided as a stack above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. A lower end of the charge accumulation layer is positioned more upwardly than a lower end of a lowermost layer-positioned one of the control gate electrodes.

Semiconductor memory device and method of manufacturing the same

According to one embodiment, a semiconductor device includes a foundation layer, a stacked body provided on the foundation layer, the stacked body including a plurality of electrode layers stacked with an insulator interposed, a semiconductor body extending through the stacked body in a stacking direction of the stacked body, and a charge storage portion provided between the semiconductor body and the electrode layers. The semiconductor body includes a first semiconductor film, and a second semiconductor film provided between the first semiconductor film and the charge storage portion. An average grain size of a crystal of the second semiconductor film is larger than an average grain size of a crystal of the first semiconductor film.

Semiconductor device and method for manufacturing semiconductor device

According to one embodiment, a semiconductor device includes a semiconductor layer; an electrode layer; a first insulating film; a charge storage film; and a second insulating film. The first insulating film is provided between the electrode layer and the semiconductor layer. The charge storage film is provided between the first insulating film and the electrode layer. The charge storage film includes a charge trapping layer and a floating electrode layer. The floating electrode layer includes doped silicon. The second insulating film is provided between the floating electrode layer and the electrode layer.

Semiconductor device and method for manufacturing the same

Method of manufacturing semiconductor memory device having charge accumulation layer positioned between control gate electrode and semiconductor layer

According to one embodiment, a non-volatile memory device includes a plurality of electrodes, at least one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film contacts the conductive layers, and extends in the first direction along the semiconductor layer between the conductive layers and the semiconductor layer. The second insulating film is provided between the first insulating film and the semiconductor layer. The first insulating film includes a first portion located between the conductive layers and the second insulating film, and a second portion located between the interlayer insulating film and the second insulating film.

Non-volatile memory device

A pressure control device according to an embodiment includes a solenoid portion for regulating a gate opening of a valve through a first shaft portion connected to the valve, a micrometer for regulating the gate opening through the first shaft portion and a second shaft portion having an axial direction which is parallel with that of the first shaft portion when the second shaft portion is connected to the first shaft portion, and a switching portion. The switching portion switches to cause the solenoid portion to regulate the gate opening or to cause the micrometer to regulate the gate opening.

Pressure control device

According to one embodiment, a semiconductor memory device includes an insulating film with a recess formed in an upper surface, and a conductive film provided on the insulating film and containing silicon, carbon and an impurity serving as an acceptor or donor for silicon. Carbon concentration of a first portion of the conductive film in contact with the insulating film is lower than carbon concentration of a second portion of the conductive film located in the recess and being equidistant from the insulating film placed on both sides thereof.

Semiconductor memory device and method for manufacturing the same

According to one embodiment, a method for fabricating a semiconductor device including a memory cell portion and a select gate portion, the method includes etching a charge accumulation layer, a tunnel insulating film, and a semiconductor substrate to make a trench, burying a first insulating film in the trench to contact with a side surface of the charge accumulation layer, performing heat processing to compress the first insulating film, forming a second insulating film on the charge accumulation layer and the first insulating film, etching the second insulating film in the select gate portion to expose a surface of the charge accumulation layer, forming a silicon layer to contact with the exposed surface of the charge accumulation layer, forming a metal layer on the silicon layer, and performing heat processing to silicide an entire boundary region between the charge accumulation layer and the tunnel insulating film.

Method for fabricating semiconductor device

A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150&#xb0; C. and satisfies a relationship of y&#x2266;1E-5exp (21541/T).

Manufacturing method for semiconductor device and semiconductor device

In a vertical diode, an N-type layer, an N-type layer, and a P-type layer are stacked in this order on a lower electrode film, and an upper electrode film is provided thereon. The effective impurity concentration of the N-type layer is lower than the effective impurity concentrations of the N-type layer and the P-type layer. At least one of the N-type layer, the N-type layer, and the P-type layer is formed from a small grain size polycrystalline semiconductor whose each crystal grain does not penetrate each layer through its thickness.

Growing community of inventors

Kuwana, Japan

Takuo Ohashi