Other

Hitachi, Ltd.

Elpida Memory, Inc.

Hitachi Tohbu Semiconductor, Ltd.

Takuo Iizuka

Hiroaki Ikeda

Yoji Nishio

Toshio Sugano

Kayoko Shibata

Seiji Funaba

Masayuki Sorimachi

A maximum value of the number of mounted memory devices is assumed, and a value of an external delay replica is fixed and set. A desired frequency band is divided into a plurality of sub-frequency bands, and delay times of an output buffer and an internal delay replica are switched and used every sub-frequency band, thereby setting an actual maximum value and an actual minimum value to the internal delay replica. A selecting pin can select the delay time in the internal delay replica. Thus, it is possible to sufficiently ensure a set-up time and a hold time of an internal clock signal generated by a delay locked loop circuit in the latch operation in a register within a desired frequency band and with a permittable number of memory devices, irrespective of the frequency level and the number of mounted memory devices.

Register capable of corresponding to wide frequency band and signal generating method using the same

First and second pre-processing flip-flops latch a command/address signal inputted to a register by a clock having a frequency of &frac12; of an external clock signal and an inverse clock thereof. Thus, the command/address signal is decomprossed to a set of signals which temporarily has two times. For example, one of the set of signals has only data contents of an odd-th command/address signal, and the other has only data contents of an even-th command/address signal. Since the set of signals has twice periods of the command/address signal, first and second post-processing flip-flop can latch signals in accordance with an internal clock signal generated by a delay locked loop circuit in a state in which a set-up time and a hold time are sufficiently assured.

Register without restriction of number of mounted memory devices and memory module having the same

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Gunma, Japan

Takuo Iizuka