Hitachi, Ltd.

Hitachi High-tech Corporation

Takumi Uezono

Tadanobu Toba

Kenichi Shimbo

Masahiro Shiraishi

Satoshi Nishikawa

Hideo Harada

Yutaka Uematsu

Yusuke Kanno

Keisuke Yamamoto

Toru Motoya

Goichi Ono

Yusuke Seki

Masato Kamio

Hironori Itabashi

Hiroki Kannami

Keisuke Tanuma

Satoru Akasaka

Fumihiko Nagasaki

Hiroaki Itsuji

It is aimed to properly correct the various types of distortion without a reduction in observation throughput. The present disclosure provides a charged particle beam device that obtains an image by irradiating a specimen with a charged particle beam and includes: a deflection coil that scans the charged particle beam on the specimen; a D/A converter that converts a digital scan waveform into an analog scan waveform and outputs the analog scan waveform to the deflection coil to drive the deflection coil; and a scan waveform generation unit that generates a digital scan waveform and outputs the digital scan waveform to the D/A converter, in which the scan waveform generation unit has a basic LUT that stores parameters for correcting the digital scan waveform and includes a correction circuit that corrects a distortion characteristic of the deflection coil.

Charged particle beam device and scan waveform generation method

The subject is to provide a technique of dealing with an internal state of a controller in an edge device by cooperation between an edge device and a computer such as a cloud server, and to generalize data communication for the cooperation and reduce an amount of data communication. Provided is a distributed system including an edge device and a diagnostic data computer. The edge device includes an in-edge controller including at least a processing unit, and a system element to be monitored by the in-edge controller. The processing unit diagnoses presence or absence of an abnormality in the processing unit due to an abnormality occurring in the system element, generates first diagnostic data indicating presence or absence of the abnormality of the processing unit, converts the first diagnostic data into second diagnostic data indicating a type of the abnormality of the processing unit, and transmits the second diagnostic data to the diagnostic data computer.

Distributed system and data transmission method

It is possible to reduce the amount of data transmitted from the edge system to the outside while securing the amount of information necessary for purposes such as factor analysis and diagnosis and the cycle of information acquisition. A distributed system includes: an edge device that is a moving body or equipment capable of automatic operation; and a diagnostic data computer. The edge device has: at least one of a movement mechanism and an actuation mechanism for implementing automatic operation; a component corresponding to at least one of the movement mechanism and the actuation mechanism; and an intra-edge controller that controls the component. The intra-edge controller reads state data acquired in the component, aggregates the read state data into component-level state data, determines an allowable latency when transferring the component-level state data to a transfer destination according to a predetermined rule, and transfers the component-level state data to the diagnostic data computer based on the allowable latency.

Distributed system and data transfer method

The operational continuity of a programmable device, and a controller using the same is enhanced. A programmable device is configured with: an error check mechanism that detects, and notifies an error from redundantized user logic blocks; a previous value retaining section that is connected to an output terminal of a last user logic block, and takes in, and outputs an output value of the user logic blocks in each control period; a CRAM check section that receives a scan interrupt due to an error occurrence notification received from the error check mechanism, reads a scan region on the CRAM, implements error detection, and error correction, and notifies a success or failure of the error correction; and an error handling section that transmits an instruction for retaining a previous output of the user logic blocks to the previous value retaining section when the error occurrence notification is received, transmits an instruction for cancelling previous-value retention to the previous value retaining section, and also transmits a logical reset instruction to a user logic block relevant to an error when a notification of a success of the error correction is received from the CRAM check section.

Programmable device, and controller using the same

To detect a discrimination error in a type of an object. A calculation system includes a first device and a second device. The first device includes: a first object map generation unit configured to calculate, using first image information that is image information acquired by the first device, a first object map indicating a type of an object and a position of the object; and a first communication unit configured to transmit the first object map to the second device. The second device includes: a second object map generation unit configured to calculate, using second image information that is image information acquired by the second device, a second object map indicating a type of an object and a position of the object; and a comparison unit configured to compare the first object map and the second object map.

Calculation system and calculation method

Learning data of a usage environment can be efficiently collected. A recognition apparatus includes: a first neural network configured to receive input of data; a second neural network configured to receive input of the data, the second neural network having a different structure from a structure of the first neural network; a comparison unit configured to compare a first output result of the first neural network and a second output result of the second neural network; and a communication unit configured to wirelessly transmit the data to a host system configured to learn the data when a comparison result between the first output result and the second output result is different by a predetermined standard or more.

Recognition apparatus and learning system using neural networks

A verification method for an application logic provided with one or more macro logics configured to perform a predetermined operation, a macro operation control unit configured to instruct the one or more macro logics to start the operation to cause the one or more macro logics to perform the operation, and an operation data storage area configured to store data. In the application logic, static verification by property description of a formal verification language is performed for each of the one or more macro logic, the macro operation control unit, and the operation data storage area, and dynamic verification by simulation is further performed for at least one of the one or more macro logics.

Application logic, and verification method and configuration method thereof

Provided is a semiconductor LSI design device that includes: a unit that generates a combinational circuit constituted by combining function blocks defined by a function block library from an application specification, by assigning connection information on an operation order of the function blocks; a unit that converts the combinational circuit to operation order information that is applicable to a sequential circuit in which a function block is used a plurality of times in a time-division manner; a unit that inversely converts the generated operation order information to a combinational circuit; a unit that verifies logical equivalence of the combinational circuit and the inversely converted combinational circuit; and a unit that combines the operation order information, the sequential circuit and a function block.

Semiconductor LSI design device and design method

The present invention includes a drawing data generating unit, a variation pattern that varies at regular intervals to be displayed, a display unit that displays drawing data, and a comparator that compares whether input signals are coincident, and the drawing data generating unit includes a receiver that receives data from a higher-level device, a drawing control unit that converts the data received from the higher-level device to drawing data, and a drawing memory that stores the drawing data. The drawing data generating unit and the variation pattern are redundantly configured, and the variation pattern is input to the drawing data generating unit. One output signal of the drawing data generating unit regarding drawing data including the variation pattern is transmitted to the display unit, a plurality of output signals from the drawing data generating unit are input to the comparator, and the comparator outputs a comparison result as a detection signal outside. This improves safety and reliability when severe safety criteria are required such as in a case of monitor-display in industrial plant equipment.

Display device

Neutron soft error rate derivation is calculated from data at the low energy neutron radiation. An outline value of an SEU cross-section function corresponding to a given neutron energy value is outputted. This outline value and the low energy neutron spectrum data are used to calculate an error count basic value of errors to occur over time. An error count actual measurement value over time is calculated from an error count during radiation of low energy neutrons and low energy neutron radiation time. The error count basic value and the error count actual measurement are used to calculate a proportionality coefficient of the SEU cross-section function. While holding a natural neutron spectrum, an error rate calculator outputs a neutron flux corresponding to a neutron energy value. The neutron soft error rate is calculated by an integration operation of multiplying the SEU cross-section function with the natural neuron spectrum.

Soft error rate calculation device and calculation method for semiconductor large scale integration (LSI)

Provided is a technology capable of reducing the number of resources necessary for logic implementation in a control device. A semiconductor LSI design device generates a combinational circuit configured with functional blocks defined by a functional block library from an application specification, allocates an operation order of each functional block in the combinational circuit under a condition for starting an operation of a functional block connected to an input pin after ending the operation, converts into a sequence circuit which uses the functional block twice or more in a time division manner, extracts the operation order at a time of execution of the sequential circuit, and determines whether the operation order allocated to the combinational circuit coincide with the extracted operation execution order.

For a soft error of an electronic device, a technique capable of ensuring high reliability because of a low soft error rate (SER) is provided. By using building data including information of a structural object of a building and facility data including information of a plurality of facilities including an electronic device arranged in the building, a SER calculating device calculates a model including an attenuation index value representing a degree of attenuation of radiation entering the building attenuated by the structural object of the building until the radiation reaches a position of the facility arranged in the building, calculates a SER at each position of the facility arranged in the building by using the model including the attenuation index value, and outputs information including the SER at each position of the facility.

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Tokyo, Japan

Takumi Uezono