Fujitsu Corporation

Fijitsu Limited

Takumi Takeno

Takato Noda

Yoshio Hirose

Takumi Kishino

Yasutomo Sakurai

Koichi Odahara

Kenichi Nabeya

Toru Watabe

Shinya Katoh

Daisuke Ban

Junya Matsushima

Kazuhiro Nonomura

Takaharu Ishizuka

Masanao Fujii

Fumitake Sugano

Katsunori Takeshita

Takao Sekiya

Hiroyasu Fujiwara

Yasuhide Shibata

A task circumstance processing system includes a processor that executes a process. The process includes: referencing a recognition information stored in a memory, the recognition information stores, for each of plural task processes in task definitions defining relationships between the plural task processes, recognition information for recognizing execution of each of the plural task processes, and extracting for each of the task processes a timing where the recognition information is expressed in observation data from observing circumstances of the task; and outputting a result of comparing a relationship between plural task processes that have been executed as identified by the extracted timings, against a relationship between plural task processes defined by the task definitions stored in the memory.

Task circumstance processing device and method

The present invention prevents, at high speed, a malfunction from occurring at the time of changing a mode in a processor, in which information to be decoded varies with modes. The processor is provided with a circuit for referring to a result of decoding information or issuing an instruction when a write operation is performed on a register for storing data containing a bit that indicates a current mode, and for outputting a purge signal if the result of decoding information or issuing an instruction is information represented by a mode switching signal. Thus, when a mode switching signal is written to the register, a purge signal is outputted to a cache memory. Consequently, the valid bit of prefetched cache data is turned off. This prevents prefetched data from being decoded in a different mode. As a result, operations are normally performed after the switching of the mode. Alternatively, the purge signal is outputted by detecting a change in the value of the bit indicating the current mode.

Processor having cache purge controller

A processor is adapted to support a complex instruction set without making major modifications to the existing hardware but by adding just a few controls and thereby emulating instructions in hardware. The processor is implemented by adding, to the existing processor, a second instruction decoder for decoding an expanded instruction code not capable of issuing an instruction per cycle, and for issuing one instruction per cycle by translating the expanded instruction code into a sequence of basic instructions; a counter for counting the number of instructions to be issued by the second instruction decoder, and for outputting a signal indicating that the expanded instruction code is being executed; and an instruction selection unit for selecting the instruction issued from the first instruction decoder when executing a basic instruction code and the instruction issued from the second instruction decoder when executing the expanded instruction code.

Processor

Processing units each having a first memory and a system controller are interconnected over a bus. The system controller includes access control units for controlling access to copies of tags of the first memories in the processing units and access to second memories to which a plurality of ways lead, and thus controls access to memories or memory access requested by the processing units. In the information processing system, a plurality of memory interfaces are included for enabling access to the second memories on an interleaving basis. Furthermore, the same numbers of copies of tags and memory access control units as the number of memory interfaces are included for enabling access to tags on the interleaving basis. Since access to the memories and tags on the interleaving basis is thus enabled, even if the number of processing units increases, competition for the memory access control units subsides and the efficiency of memory access improves.

Information processing system in which memory devices and copies of tags are accessed in response to access requests issued from plurality of processing units

A TMR unit connects a plurality of processors by a bus and simultaneously executes the same processing operation. Among the plurality of processors, one of them is a master and the remaining processors are slaves. Information formed by only the master processor is outputted to the bus. Each processor has a multiplex control circuit. The multiplex control circuit compares output information formed by itself with bus information outputted to the bus, thereby detecting a failure and allowing an internal circuit to execute necessary processes.

Information processing system

Growing community of inventors

Kawasaki, Japan

Takumi Takeno