Fujitsu Corporation

Fujitsu Semiconductor Limited

Takumi Danjo

Sanroku Tsukamoto

Hirotaka Tamura

Yutaka Kai

Masanori Hoshino

Akihiko Kasagi

Takashi Arakawa

Takeshi Takayama

Masakatsu Ito

A non-transitory computer-readable recording medium storing a calculation processing program for causing a computer to execute processing, the processing including: calculating error gradients of a plurality of layers of a machine learning model that includes an input layer of the machine learning model at the time of machine learning of the machine learning model; selecting a layer of which the error gradient is less than a threshold as a suppression target of the machine learning; and controlling a learning rate and performing the machine learning on the layer selected as the suppression target in a certain period of time before the machine learning is suppressed.

Computer-readable recording medium storing machine learning program, machine learning method, and information processing device of improving performance of learning skip in training machine learning model

A deep learning method is performed by a computer having a plurality of nodes. The method comprises measuring, in learning performed by using the plurality of nodes in deep learning, performance of each of the nodes, allocating a number of batches to be processed by an entirety of the plurality of nodes to the individual nodes in accordance with the respective performance measured, and processing the allocated batches in each of the nodes.

Calculator, deep learning method and computer-readable recording medium storing program for deep learning

An arithmetic processing apparatus includes: a plurality of nodes (N nodes) capable of communicating with each other, each of the plurality of nodes including a memory and a processor, the memory being configured to store a value and an operation result, the processor being configured to execute first processing when N is a natural number of 2 or more, n is a natural number of 1 or more, and N&#x2260;2, wherein the first processing is configured to divide by 2 a value held by a first node, the first node being any of the plurality of nodes and a last node in an order of counting, obtain one or more node pairs by pairing remaining nodes among the plurality of nodes exception for the first node, and calculate repeatedly an average value of values held by each node pair of the one or more node pairs.

Arithmetic processing apparatus, control method of arithmetic processing apparatus, and non-transitory computer-readable storage medium for storing program

An information processing system includes: a first information processing device that transmits first data to be retained via a communication path; a second information processing device that calculates first calculation result data that is a calculation result of the first data received via the communication path and second data to be retained and transmits the calculated first calculation result data via the communication path; a third information processing device that transmits third data to be retained via the communication path; and a fourth information processing device that calculates second calculation result data that is a calculation result of the third data received via the communication path and fourth data to be retained and calculates third calculation result data that is a calculation result of the first calculation result data received via the communication path and the calculated second calculation result data.

Information processing system and control method of information processing system

Boltzmann machine includes a plurality of circuit units each having an adder that adds weighted input signals and a comparison unit that compares an output signal of the adder with a threshold signal to output a binary output signal; and digital arithmetic units each generating the weighted input signals by weighting the binary output signal of the circuit units with a weight. The comparison unit has a first comparator that compares a thermal noise with a reference voltage to output a binary digital random signal, a DA converter that converts the digital random signal to an analog random signal and varies a magnitude of the analog random signal, and a second comparator that compares the output signal of the adder with the analog random signal to generate the binary output signal with a predetermined probability function.

Boltzmann machine, method for controlling boltzmann machine, and information processing device having boltzmann machine

A comparator system includes: a clock node configured to supply a clock signal; a comparator configured to compare a signal of a first input node with a signal of a second input node in synchronization with the clock signal; and a first variable capacitance coupled between the first input node and the clock node.

Comparator system

An electronic circuit includes: a pair of first transistors in which a first control signal is inputted to at least one of a first control terminal; a comparator circuit that sets electric potentials of a pair of differential output terminals based on an electric current flowing through the pair of first transistors; second transistors that are coupled in series in a path between an electric power source and a node from at least one of the pair of differential output terminals and between the corresponding pair of first transistors, and having a second control terminals to which a second control signal is inputted; first switches that are respectively coupled in series to the second transistors in the path and that are turned ON in synchronization with a clock signal; and a generation circuit that generates the second control signal based on the clock signal.

Electronic circuit

A folded cascode amplifier circuit includes: an input stage having a pair of transistors and configured to output a positive phase intermediate signal and an opposite phase intermediate signal; a cascode amplification stage having pairs of transistors connected in multiple stages, to which the positive phase intermediate signal and the opposite phase intermediate signal are supplied, and which is configured to output a positive phase output signal and an opposite phase output signal, which are differential signals; a first capacitor connected between a signal line of the positive phase intermediate signal and a signal line of the opposite phase output signal; and a second capacitor connected between a signal line of the opposite phase intermediate signal and a signal line of the positive phase output signal.

Folded cascode amplifier circuit

A comparator has a comparator circuit to output an output voltage based on a voltage difference between a first and second input voltage, a variable capacitor connected to an output terminal, an input voltage control circuit to generate a common voltage and add the common voltage to the first and the second input voltages, and a correction circuit to control the variable capacitor to control the common voltage. The correction circuit controls a first capacitance value of the variable capacitor so that the output voltage is reversed when the voltage difference equals a first voltage difference, and controls a second capacitance value of the variable capacitor so that the output voltage is reversed when the voltage difference equals a second voltage value, and controls the common voltage so that a difference between the first capacitance value and the second capacitance value becomes equal to a predetermined capacitance value.

Comparator and correction method therefor

A comparator includes: a differential amplifier of which operational state is switched in response to a clock-signal, and which outputs a first intermediate-output corresponding to a first input-signal and a second intermediate-output corresponding to a second input-signal; a differential latch circuit of which operational state is switched in response to the clock-signal, and a state of which is changed depending on the first intermediate-output and the second intermediate-output; a first adjuster configured to adjust a threshold of the differential latch circuit with respect to a change of a state of the first intermediate-output and a change of a state of the second intermediate-output; and a second adjuster configured to adjust a threshold variation of the differential latch circuit with respect to a change of a state of the first intermediate-output and a change of a state of the second intermediate-output.

Comparator and A/D converter

A comparator includes: a differential amplifier circuit to operate based on a clock signal and output a first intermediate output and a second intermediate output corresponding to a first input signal and a second input signal respectively; and a differential latch circuit to operate based on the clock signal and vary a state based on the first intermediate output and the second intermediate output, the differential latch circuit having a controllable sensitivity with respect to a state variation of the first intermediate output and the second intermediate output.

Compapator and analog-to-digital convertor

Various embodiments of an analog-to-digital (A/D) device are described herein, with the A/D device using at least a comparison unit, a comparative operation control circuit, a delay circuit, and a successive operation control circuit arranged so as, it may, among other things, mitigate conversion errors that may be due to differences in properties of circuit elements therein. And the A/D device may be implemented in, among other things, a signal processing device.

Comparison circuit and analog-to-digital conversion device

An analog-to-digital conversion circuit includes: comparators to compare an input analog signal and one of reference voltages corresponding to each operation in an analog-to-digital conversion; an interpolating comparator to compare the input analog signal and a determination voltage between first and second reference voltages corresponding to two comparators; a correction value acquisition circuit to calculate a correction value to correct an error between the input analog signal and the determination voltage; a correction value application circuit to set the correction value in the interpolating comparator; a test voltage generation circuit to supply the two comparators with a first test voltage corresponding to one of the determination voltages; a common voltage generation circuit to supply the two comparators with a second test voltage; and a correction value calculation circuit to calculate respective correction values corresponding to the determination voltages based on errors corresponding to the first and second test voltages.

A/D conversion circuit and A/D conversion method

An amplifying circuit includes a pair of MOS transistors; an amplifier that amplify a difference between potentials of differential output nodes coupled to drains of the pair of MOS transistors; cancel circuits that cause cancel current to flow to one of the differential output nodes when the amplifier amplifies a voltage between the differential output nodes and that shut off, after the amplifier performs the amplification operation, inflow of the cancel current; and a controller that performs setting so that a potential of first one of the differential input signals is equal to a potential of another one of the differential input signals, that compares, before the inflow of the cancel current, potentials generated at differential output nodes when the difference between potentials of the differential output nodes is amplified, and that sets the cancel current so that the potentials are reversed after the inflow of the cancel current.

Amplifying circuit and analog-digital converting circuit including same

A comparison circuit includes: an input circuit includes a first transistor for receiving a first signal, and a second transistor for receiving a second signal; a first current route of which the electric current is controlled by the first transistor; a second current route of which the electric current is controlled by the second transistor; a latch for amplifying potential difference between the first current route and the second current route; a comparative operation control circuit including a first switch for executing or blocking supply voltage to the drain of the first transistor, a second switch for executing or blocking supply voltage to the drain of the second transistor, and a third switch for executing supply voltage to the first current route and the second current route; a comparative operation setting circuit for controlling supply or blocking of supply of the first switch, the second switch, and the third switch.

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Kawasaki, Japan

Takumi Danjo