Kabushiki Kaisha Toshiba

Takumi Abe

Koichi Fukuda

Hiroshi Maejima

Rieko Tanaka

Takahiko Hara

Ken Takeuchi

Katsuaki Isobe

Makoto Hamada

A nonvolatile semiconductor memory device including a memory cell configured to store data and a resistor element provided around the memory cell. The memory cell includes a charge storage layer provided above a substrate, a first semiconductor layer formed on a top surface of the charge storage layer via an insulating layer, and a first low resistive layer formed on a top surface of the first semiconductor layer and having resistance lower than that of the first semiconductor layer. The resistor element includes a second semiconductor layer formed on the same layer as the first semiconductor layer, and a second low resistive layer formed on the same layer as the first low resistive layer and on a top surface of the second semiconductor layer, having resistance lower than that of the second semiconductor layer.

Nonvolatile semiconductor memory device and method of manufacturing the same

A nonvolatile semiconductor memory device comprises a memory cell configured to store data and a resistor element provided around the memory cell. The memory cell includes a charge storage layer provided above a substrate, a first semiconductor layer formed on a top surface of the charge storage layer via an insulating layer, and a first low resistive layer formed on a top surface of the first semiconductor layer and having resistance lower than that of the first semiconductor layer. The resistor element includes a second semiconductor layer formed on the same layer as the first semiconductor layer, and a second low resistive layer formed on the same layer as the first low resistive layer and on a top surface of the second semiconductor layer, having resistance lower than that of the second semiconductor layer.

A semiconductor memory device includes a sense amplifier which senses identical multilevel data, which is stored in a memory cell, a plurality of number of times at a time of read, and a n-channel MOS transistor which has a current path one end of which is connected to the sense amplifier and the other end of which is connected to a bit line. The device further include a control unit which applies a first voltage to a gate electrode of the n-channel MOS transistor, thereby setting the n-channel MOS transistor in an ON state, and applies a second voltage which is higher than the first voltage, to the gate electrode during a period after first sense and before second sense.

Semiconductor memory device

The nonvolatile semiconductor memory device related to an embodiment of the present invention includes a cell array including a memory string, a bit line connected to the memory string, a first wire connected to a cell source line of a memory cell, a second wire connected to a cell well line of a memory cell, a third wire which supplies a power supply voltage to a circuit arranged outside of a region of the cell array, a fourth wire and a fifth wire being arranged in a row direction within the cell array region, and the first wire, the second wire and the third being formed in a layer above a layer in which the bit line within the cell array is formed, the fourth wire and the fifth wire being formed in the layer in which the bit line within the cell array region is formed.

Nonvolatile semiconductor memory device

A semiconductor memory device includes a plurality of memory cells, signal lines, and a control unit. Each of the plurality of memory cells includes a charge storage layer. Each of the plurality of memory cells includes a control gate and is configured to hold two-or-higher-level data. Each of signal lines is electrically connected with a gate or one end of a current path of each of the memory cells. Each of signal lines has a line width which differs depending on each interval between the memory cells adjacent to each other. The control unit controls a voltage applied to each of the signal lines in accordance with the line width of each of the signal lines.

Semiconductor memory device including charge storage layer and control gate

A semiconductor memory device according to an embodiment of the present invention includes a resistance element which is constructed with a first conductor which extends in a first direction and is connected to a first contact; a second conductor which extends in said first direction and is connected to a second contact; and a first insulation film which exists between said first conductor and said second conductor, said first insulation film also having an opening in which a third conductor which connects said first conductor and said second conductor is arranged.

Semiconductor memory device having resistance element with two conductors

A NAND-structured flash memory including a selection transistor having a first conducting path, one end of the first conducting path being connected to a bit line or a source line, at least one dummy gate having a second conducting path and a control gate, one end of the second conducting path being connected to the other end of the first conducting path of the selection transistor, a nonvolatile memory linked unit for storing external data, which includes a plurality of electrically erasable/writable nonvolatile memory cells having third conducting paths and control gates, the third conducting paths being connected in series, one end of the series of the third conducting paths being connected to the other end of the second conducting path of the dummy gate, a dummy gate driving circuit controlling a potential of the control gate of the dummy gate, and a memory cell driving circuit selectively driving the control gates of the plurality of nonvolatile memory cells to write, read or erase bit data for storing the external data.

Nand-structured flash memory

A nonvolatile semiconductor memory includes a memory cell array including horizontally aligned memory cell columns, each including vertically arranged memory cell transistors and select transistors selecting the memory cell transistors; first cell well lines connecting well regions in which the memory cell columns are formed; second cell well lines arranged in an interconnect layer above the first cell well lines and connecting the first cell well lines to one another electrically; and a cell source line connecting source terminals of the select transistors in each memory cell column.

Nonvolatile semiconductor memory having a plurality of interconnect layers

A memory cell array in a semiconductor substrate has a plurality of memory cells arranged in rows and columns. A first circuit is located at one end of the memory cell array in a column direction. A second circuit is located at the other end of the memory cell array in the column direction. A first wire is located above the memory cell array between the first circuit and the second circuit. The first wire is located in a most upper layer in the semiconductor substrate to supply power to the second circuit.

Semiconductor memory device with power supply wiring on the most upper layer

A NAND type flash memory included with a memory cell array composed of a plurality of electronically rewritable memory cells arranged in a matrix shape, and a data inversion control section which judges whether a polarity of a '1' data or a '0' data is to be inverted based on the number of the &#x201c;1&#x201d; data and the &#x201c;0&#x201d; data of the data when data is sent to the plurality of memory cells within a simultaneous write data unit and inverts the data and in the case where it is sent to the memory cell array adds an inversion flag bit to the data which shows the inversion of the polarity.

NAND type flash memory

A NAND-structured flash memory comprises a memory cell array wherein plural memory strings are arranged in matrix form, each of the memory cell strings including plural nonvolatile memory cells, the first conducting paths of the memory cells being connected in series, at least one of the memory cells having a function other than an external data storing function, plural first selection transistors having second conducting paths, and one end of the second conducting paths being connected to one end of the series of the first conducting paths, respectively, plural bit lines connected to the other end of the second conducting paths, plural second selection transistors having third conducting paths, and one end of the third conducting paths being connected to one end of the series of the first conducting paths, respectively, and a source line connected to the other end of the third conducting paths.

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Mountain View, CA, United States of America

Takumi Abe