Fujitsu Corporation

Nippi Corporation

Takuji Yamamoto

Hiroshi Hamano

Takeshi Ihara

Izumi Amemiya

Naoki Kuwata

Shigeto Suzuki

Yoshinori Nishizawa

Yasunari Arai

Takashi Shiraishi

Michiko Shiraga

Hiroki Ooi

George Ishikawa

Hiroyuki Fukuda

Yoichi Oikawa

Hiroshi Endo

Hiroshi Nakamoto

Masazumi Marutani

Shunji Hattori

Michael G Lee

Satoshi Kuroyanagi

Takayuki Shibasaki

Kouichi Kanda

Masaya Kibune

Hiroshi Nakao

Hiroyuki Rokugawa

Yoshiyasu Doi

Teruo Ishihara

Koichi Shirahata

Hiroo Kitasagami

Hisanao Akima

Shinkichi Irie

Masayuki Hiromoto

Katsuya Yamashita

Kiyonori Higa

Yuko Ushiki

A computer includes: a memristor array including memristors arranged at intersections between word lines and a first bit line in the memristor array and at intersections between the word lines and second bit lines in the memristor array; an adder circuit configured to obtain sum voltages for the second bit lines by adding first voltages generated according to currents that flow in the second bit lines when a first pattern is supplied to the word lines to difference voltages between a reference voltage generated according to a current that flows in the first bit line when a second pattern is supplied to the word lines and second voltages generated according to currents that flow in the second bit lines when a second pattern is supplied to the word lines; and a detection circuit that detects a second bit line that corresponds to a maximum value of the sum voltages.

Computer and calculation method using memristor array

A power estimation method includes acquiring first consumed power information indicating a change in power consumed for a first time period from a first time to a second time within a time period elapsed from the start of the execution of a first job, and second consumed power information indicating a change in power consumed for a second time period from a third time to a fourth time within the time period elapsed from the start of the execution of the first job, the third time being after the second time, generating, from the first consumed power information, a first estimation model for estimating power to be consumed by the job for the first time period, and generating, from the second consumed power information, a second estimation model for estimating power to be consumed by the job for the second time period.

Storage medium, job power estimation method, and job power estimating device

A non-transitory computer-readable recording medium has stored therein a program that causes a computer to execute a process including: dividing a time from a start to an end of execution of a first job into a plurality of time periods, the time being represented in first power consumption information; calculating a cycle of a time-series variation of power consumption within each time period; generating, for each of the plurality of time periods, a prediction model for predicting power consumption of a predetermined future time; acquiring second power consumption information that is an actual measurement value of power consumption according to an elapsed time from a start of execution of a second job that is being executed; and predicting future power consumption of the second job, using the prediction model generated for a time period including the elapsed time from the start of execution of the second job to a present.

Job power predicting method and information processing apparatus

An apparatus calculates, based on attribute information of a new job and jobs that have been executed, a first similarity level of the attribute information between the new job and the jobs by using a calculation expression, identifies a job whose attribute information is most similar to that of the new job as a first candidate job, and estimates power consumption to be consumed by the new job at power consumption of the first candidate job. The apparatus calculates, for at least one of the jobs, a second similarity level of power consumption between the at least one of the jobs and the new job, identifies a job whose power consumption is most similar to that of the new job as a second candidate job, and adjusts the calculation expression to increase the first similarity level to be calculated between the new job and the second candidate job.

Estimation of power consumption for a job based on adjusted calculation of similarities between jobs

A non-transitory computer-readable recording medium stores therein a program that causes a computer to execute a process, the process including: specifying first job information related to a new job; referring to a storage that stores second job information and power information for each of past jobs to specify a predetermined number of pieces of third job information of which matching status with the first job information satisfies a first condition; determining, for each piece of the third job information, whether a matching status with the first job information satisfies a second condition; specifying one piece of the third job information based on a determination result; specifying power information associated with the one piece of the third job information; correcting the specified power information in accordance with the determination result; and estimating power information indicating power consumption at a time of executing the new job based on the corrected power information.

Information processing apparatus and power estimation method

An interposer for an electronic circuit chip package may include a substrate, a recess, first conductive vias, and second conductive vias. The substrate may have a first surface, a second surface substantially parallel to and opposite the first surface, a third surface substantially parallel to the first surface and the second surface, and an orthogonal surface that is substantially orthogonal to and intersects the first surface and the third surface. The recess may be formed in the substrate and defined by the third surface and the orthogonal surface. The first conductive vias may pass from the second surface to the first surface. The second conductive vias may pass from the second surface to the third surface.

Interposer for integrated circuit chip package

Provided is a unit which is capable of readily grinding and collecting a small amount of a sample which is difficult to be ground. The unit for grinding a sample comprises a club-shaped pestle and a mortar into which the pestle can be inserted, wherein the pestle comprises a roughened taper located at at least one end of its pestle body, wherein the mortar is a tube with an inverted frustoconical bottom, and the surface of the mortar where the taper of the pestle contacts the inverted frustoconical bottom when the pestle is inserted into the mortar is roughened, and wherein the angle of the taper with respect to the longitudinal centerline of the pestle is substantially equal to the angle of the inner wall of the inverted frustoconical bottom with respect to the longitudinal centerline of the mortar. The roughened taper and surface improve grinding efficiency.

Unit for grinding sample, unit for grinding and collecting sample, and process for grinding same

A receiver includes: a first amplifier for amplifying an input signal and outputting an output signal; a clock generator for generating a clock signal corresponding to a period of the output signal; a judger for outputting a first logical value or a second logical value in accordance with a phase lead or phase lag which has been occurred at a crossing point of the positive-phase signal and the negative-phase signal of the output signal upon rising or falling the clock signal; a detector for outputting a difference value between a time for which the judgment signal has the first logical value and a time for which the judgment signal has the second logical value; and an adjustor for adjusting reference voltages of a positive-phase signal and a negative-phase signal of the input signal in accordance with the difference value output from the detector.

Receiver

A receiving circuit includes: a clock generating circuit to generate a plurality of clock signals in a cycle; an oversampling circuit to oversample input data based on the plurality of clock signals and output a plurality of samples of digital data in a unit interval; a data boundary determining circuit to detect a changing point of the digital data, determine data boundaries of the unit interval based on the changing point, and output digital data corresponding to a central data between the data boundaries; and a clock phase control circuit to control a phase of at least one of the plurality of clock signals so that a first number of the plurality of samples becomes a certain value when a second number of samples between the data boundaries is larger than a threshold value.

Receiving circuit and sampling clock control method

An amplifier is realized by a distributed-constant-type amplifier including an input-side transmission line and an output-side transmission line, and a plurality of unit circuits coupled between the input-side transmission line and the output-side transmission line, in which each of the plurality of unit circuits is formed by including an amplification circuit having a gain equal to or greater than one.

Amplifier

The invention concerns an optical transmitter and receiver, and provides an improved timing extraction circuit for use in an optical receiver that uses a clock of a frequency equal to one half the data transmission rate, and a duty cycle deviation handling circuit for use in the optical transmitter and receiver. The timing extraction circuit uses a PLL circuit containing a phase comparator circuit for performing a phase comparison between a data signal of bit rate B (bits/s) and a clock signal of B/2 (Hz) at intervals of 2/B (sec), and comprises: a detection circuit for detecting the absence of an output of phase comparison information from the phase comparator circuit by receiving a data signal of a prescribed pattern; and a control circuit for controlling, upon detecting the absence, the phase of the clock signal in order to maintain synchronization. Based on the result of evaluating the duty cycle between the input data before and after the point at which the PLL circuit is locked, the duty cycle deviation handling circuit controls the data discrimination phase before and after that point.

Timing extraction circuit for use in optical receiver that uses clock of frequency equal to one half of data transmission rate, and duty cycle deviation handling circuit for use in optical transmitter and receiver

The present invention provides a sample breaking-up instrument and a method thereof, in which a pressing member is pressed by a centrifugal force against a sample within a cylindrical body provided with a filter member to thereby break-up the sample safely and efficiently. Provided is an instrument for breaking-up a sample, comprising: a cylindrical body having a through hole opening in both ends thereof; a filter member installed in one end of the cylindrical body within the through hole; and a pressing member to be operatively inserted into the hole of the cylindrical body from the other end thereof so as to be slidable therethrough in a sealed manner, wherein a force is exerted on the pressing member so that the pressing member presses the sample placed between the pressing member and the filter member against the filter member and thereby the sample is forced to pass through the filter member and is thus broken-up.

Instrument and method for breaking-up sample

An optical dispersion monitoring apparatus and an optical dispersion monitoring method are capable of monitoring dispersion accurately with a simple construction in an optical transmission system using the same. To this end, the optical dispersion monitoring apparatus includes a light receiving section converting an input optical signal into an electrical signal, a signal transition position detecting section detecting the voltage level of a waveform of the output signal from the light receiving section, at a crossing point of a rising edge and a falling edge, and a cumulative dispersion information extracting section comparing the voltage level at the crossing point with a reference signal to extracts cumulative dispersion information.

Optical dispersion monitoring apparatus and optical dispersion monitoring method, and optical transmission system using same

A differential amplifier suitably adapted to an ultra-high-speed signal transmitting apparatus. The differential amplifier includes a first inductor located between a differential transistor and a gate grounded transistor, an optional second inductor located between a load resistor and a power supply, and an optional third inductor located between a source follower transistor and an output terminal.

Differential amplifier

According to a PLL circuit of the present invention, an output of a phase comparator is adjusted according to a space-to-mark transition-probability of an input signal so that an output of a voltage controlled oscillator has a predetermined frequency and phase. Therefore, even when a phase of a timing clock is set other than at, an output of the PLL circuit can be kept at the set phase, irrespective of the space-to-mark transition-probability. By using the PLL circuit as such in an optical communication apparatus and an optical communication system, a discrimination point can be kept almost fixed, and therefore, it is possible to lower an error rate.

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Kawasaki, Japan

Takuji Yamamoto