Mitsubishi Denki Kabushiki Kaisha

Takuji Sonoda

Shinichi Sakamoto

Kazuo Hayashi

Nobuyuki Kasai

Tetsuya Yagi

Tatsuya Kimura

Takao Ishida

Teruyuki Shimura

Shigeru Mitsui

Saburo Takamiya

Kaoru Kadoiwa

Iwao Hayase

Koichi Narita

A bipolar transistor circuit element includes a semiconductor substrate; successively disposed on the substrate, a base layer, an emitter layer, and a collector layer; a bipolar transistor formed from parts of the collector, base, and emitter layers and including a base electrode electrically connected to the base layer and a base electrode pad for making an external connection to the base layer; a base ballasting resistor formed from a part of the base layer isolated from the bipolar transistor and electrically connecting the base electrode to the base electrode pad; and a base parallel capacitor connected in parallel with the base ballasting resistor wherein the base parallel capacitor includes part of the base input pad, a dielectric film disposed on part of the base electrode pad, and a second electrode disposed on the dielectric layer opposite the base electrode pad and electrically connected to the emitter electrode of the bipolar transistor. The base ballasting resistor has a high resistance relative to an emitter ballasting reactor so that it can be easily mass produced with good uniformity and yield.

Bipolar transistor circuit element having base ballasting resistor

An epitaxial growth apparatus includes a substrate heating member, a growth chamber, a molecular beam source, a nozzle for ejecting a gaseous source material, an exhaust pipe, and a vacuum chamber. When a gate valve is opened between the vacuum chamber and the growth chamber, gas is exhausted from the growth chamber, and the pressure in the growth chamber is rapidly reduced. The transition from a state where the degree of vacuum is low to a state where the degree of vacuum is high is performed rapidly. Therefore, one crystalline growth apparatus is sufficient for freely selecting among growth modes to achieve desired thickness and controllability of the carrier concentration in an epitaxially grown layer. One mode requires selectivity and another mode suppresses dopant concentration for epitaxial growth of layers of an optical device or of a microwave device.

Epitaxial crystal growth apparatus

A high resistance compound semiconductor layer included in a semiconductor device including a plurality of compound semiconductor layers having different compositions includes a compound semiconductor that is vapor phase grown employing an organic metal compound including In, an organic metal compound including Al, and a hydrogenated compound or an organic metal compound including As. The high resistance compound semiconductor layer includes p type impurities having a concentration that positions the Fermi level of the compound semiconductor approximately at the center of the band gap of the compound semiconductor. Therefore, it is possible to produce a high resistance AlInAs layer that has less impurities that are diffused into an adjacent compound semiconductor layer.

Method of making semiconductor device including high resistivity layer

A field effect transistor with improved operation speed and reduced noise includes a drain electrode disposed on a channel layer with a contact layer interposed therebetween, a source electrode, and a gate electrode disposed between the drain and source electrodes. A resonant tunneling diode is disposed between the source electrode and the channel region for supplying hot electrons to the channel layer beneath the gate electrode.

Field effect transistor

A semiconductor device includes a semiconductor substrate and channel and electron supply layers epitaxially grown on the semiconductor substrate. Source, drain, and gate electrodes are disposed on the electron supply layer. At least the gate electrode and the electron supply layer are structured such that an electron gas within the channel layer is one-dimensional to prevent scattering of electrons in the channel layer.

Semiconductor device and method of making it

A field effect transistor has an active layer containing a multi-step recess that becomes narrower as it approaches the substrate. A gate electrode is produced at the deepest portion of the recess section. The transistor may be produced by successively selectively etching the active layer and an overlying semiconductor surface protection film to produce a multi-step configuration recess, depositing a gate electrode at the bottom of the recess, and depositing source and drain electrodes on the active layer.

Method for producing a field effect transistor with a gate recess

A mushroom-shaped gate electrode has a lower end in a recess in a semiconductor active layer on a semiconductor substrate. The gate electrode has an enlarged head. A metallic side wall is disposed on a portion of the leg of the gate electrode adjacent the head. Thus, the gate length of a semiconductor device, such as a field effect transistor, is reduced while the effective cross-sectional area of the gate electrode is increased whereby the noise characteristics of the semiconductor device are improved.

Method of making a mushroom-shaped gate electrode of semiconductor device

A heterojunction field effect transistor includes a semi-insulating crystalline layer, a pseudomorphic channel layer disposed on the semi-insulating crystalline layer, and an electron supply layer disposed on said pseudomorphic layer. The channel layer has a lattice constant equal to or close to that of the semi-insulating crystalline layer adjacent to semi-insulating crystalline layer and different from the semi-insulating crystalline layer adjacent to the electron supply layer.

Heterojunction field effect transistor

A field effect transistor includes a GaAs substrate on which an undoped GaAs layer is disposed. A doped electron supply layer is disposed on the undoped GaAs layer and has a negligible deep dopant level. A channel layer disposed on the electron supply layer has a larger electron affinity than the electron supply layer. The electron supply layer and the channel layer form a heterojunction. A third semiconductor layer having the same conductivity type as the electron supply layer is disposed on the electron supply layer. Gate, drain, and source electrodes are disposed on the third semiconductor layer. The dopant concentration of the third layer is smaller than the dopant concentration of the electron supply layer.

Semiconductor device with a mushroom-shaped gate electrode

At least two unit transistor groups, each including unit transistors arranged along a straight line, are disposed on a substrate parallel to and facing each other. Each transistor in one group and a facing transistor in the other group have integral first, second, and control electrodes. The first, second, and control electrodes of the unit transistors are connected to associated respective electrode pads.

Monolithic parallel connected transistor structure

A semiconductor device includes a relatively broad recess in a semiconductor substrate between a source electrode and a drain electrode, a relatively narrow, deeper recess closer to the source electrode than to the drain electrode, and a T-shaped gate electrode having a broad head disposed in the narrower recess. A production method for a semiconductor device having a T-shaped gate electrode provided with a broad head and disposed in a two stage recess includes producing a relatively broad recess in a semiconductor substrate leaving a dummy gate, producing a resist pattern for producing the head of the T-shaped gate electrode, exposing the dummy gate by removing some of the resist pattern, and thereafter producing a narrower, deeper recess closer to the source electrode than to the drain electrode, thereby producing a two stage recess structure and producing a T-shaped gate electrode in the deeper recess.

Method of producing a t-shaped gate electrode

A semiconductor device includes a semiconductor body and a metal contact forming a Schottky barrier with said body, the metal contact including a layer of nickel disposed on the semiconductor body, an aluminum layer disposed on the nickel layer, and a nickel aluminum alloy disposed at the interface of the layers. The alloy is formed by heating the metal layers.

Method of making a schottky electrode

A method of producing a semiconductor device includes etching a recessed aperture in a substrate, forming a gate electrode in the aperture, burying the gate electrode with resist, etching the resist to expose the gate electrode, depositing a high conductivity metal on the gate electrode, and forming ohmic electrodes on opposite sides of the gate electrode by a series of processing steps.

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Itami, Japan

Takuji Sonoda