Renesas Electronics Corporation

Nec Electronics Corporation

Takuji Onuma

Toshiyuki Takewaki

Daisuke Oshida

Yoshitaka Kubota

Kenichi Hidaka

Hiroshi Tsuda

Hiromichi Takaoka

Koichi Ohto

Yasuaki Tsuchiya

Masayuki Hiroi

Manabu Iguchi

Toshiji Taiji

Mieko Hasegawa

Ichiro Honma

Takaharu Kunugi

Hironori Toyoshima

Hiroaki Nanba

Noriaki Kodama

Kiyokazu Ishige

Yasutaka Nakashiba

Hiroyuki Kobatake

An antifuse comprised of an NMOS transistor or an NMOS capacitor includes a first terminal coupled to a gate electrode, a second terminal coupled to a diffusion layer, and a gate insulating film interposed between the gate electrode and the diffusion layer. A programming circuit includes a first programming circuit which has first current drive capability and which performs first programming operation and a second programming circuit which has second current drive capability larger than the first current drive capability and which performs second programming operation to follow the first programming operation. In the first programming operation, the first programming circuit breaks down the gate insulating film by applying a first programming voltage between the first terminal and the second terminal. In the second programming operation, the second programming circuit applies a second programming voltage lower than the first programming voltage between the first terminal and the second terminal.

Semiconductor memory device and antifuse programming method

A first semiconductor device is formed over a substrate and includes a first insulation film, a first electrode, and a first diffusion layer. A second semiconductor device is formed over a substrate and includes a second insulation film, a second electrode, and a second diffusion layer. The second electrode is coupled to the first electrode. A control transistor allows one of a source and a drain to be coupled to the first electrode and the second electrode, allows the other one of the source and the drain to be coupled to a bit line, and allows a gate electrode to be coupled to a word line. A first potential control line is coupled to the first diffusion layer and controls a potential of the first diffusion layer. A second potential control line is coupled to the second diffusion layer and controls a potential of the second diffusion layer.

Semiconductor device having memory unit, method of writing to or reading from memory unit, and semiconductor device manufacturing method

A non-volatile semiconductor memory device having a memory cell in which operating potentials are few and the scale of the peripheral circuitry is reduced includes a select transistor having a source/drain on both sides of a channel of a semiconductor substrate and having a gate electrode disposed on the channel via a thick gate insulating film; an element isolation region formed on the semiconductor substrate in an area adjacent to the select transistor; an antifuse adjacent to the element isolation region, having a lower electrode formed on the semiconductor substrate and having an upper electrode disposed on the semiconductor substrate in an area between the element isolation region and lower electrode via a thin gate insulating film; and a connection contact electrically connecting the source and upper electrode and contacting the source and the upper electrode.

Non-volatile semiconductor memory device

An antifuse whose internal written information cannot be analyzed even by utilizing methods to determine whether there is a charge-up in the electrodes. The antifuse includes a gate insulation film, a gate electrode, and a first diffusion layer. A second diffusion layer is isolated from the first diffusion layer by way of a device isolator film, and is the same conduction type as the first diffusion layer. The gate wiring is formed as one integrated piece with the gate electrode, and extends over the device isolator film. A common contact couples the gate wiring to the second diffusion layer. The gate electrode is comprised of semiconductor material such as polysilicon that is doped with impurities of the same conduction type as the first diffusion layer. The second diffusion layer is coupled only to the common contact.

Semiconductor device with common contact coupling gate wiring integrated with gate electrode of antifuse to diffusion layer

A semiconductor device has a conventional NMOS transistor and an NMOS transistor functioning as an anti-fuse element and having an n type channel region. The conventional NMOS transistor is equipped with an n type extension region and a p type pocket region, while the anti-fuse element is not equipped with an extension region and a pocket region. This makes it possible to improve the performance of the transistor and at the same time improve the characteristics of the anti-fuse element after breakdown of its gate dielectric film.

Semiconductor device having an anti-fuse element and a transistor with a pocket region

A semiconductor device including: a substrate; an insulating film formed over the substrate; a copper interconnect, having a plurality of hillocks formed over the surface thereof, buried in the insulating film; a first insulating interlayer formed over the insulating film and the copper interconnect; a second insulating interlayer formed over the first insulating interlayer; and an electroconductive layer formed over the second insulating interlayer, wherein the top surface of at least one hillock highest of all hillocks is brought into contact with the lower surface of the second insulating interlayer is provided.

Semiconductor device and method of manufacturing the same

A method for programming an anti-fuse element in which the ratio between current values before and after writing is increased to ensure accuracy in making a judgment about how writing has been performed on the anti-fuse element. The method for programming the anti-fuse element as a transistor includes the steps of applying a prescribed gate voltage to a gate electrode to break down a gate dielectric film, and moving the silicide material of a silicide layer formed on a surface of at least one of a first impurity diffusion region and a second impurity diffusion region, into the gate dielectric film in order to couple the gate electrode with at least the one of the first impurity diffusion region and the second impurity diffusion region electrically through the silicide material.

Method for programming an anti-fuse element, and semiconductor device

A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.

Method of manufacturing semiconductor device

A semiconductor memory device includes a first anti-fuse element and a second anti-fuse element, respectively composed of a transistor, wherein the first anti-fuse element and the second anti-fuse element are configured so as to be concomitantly programmable, respectively formed in P-wells on a substrate, and the adjacent P-wells are isolated by N-wells of an opposite conductivity type, formed therebetween.

Semiconductor memory device and a method of controlling a semiconductor memory device

A method of forming a semiconductor device, includes forming a lower electrode including a metal and a nitrogen on a semiconductor substrate, irradiating a reducing gas to a surface of the lower electrode, and irradiating a gas containing silicon to the surface of the lower electrode to form a projection containing silicide by reacting the metal with the silicon in an island shape on the surface of the lower electrode. Then, a capacitor film is formed on the lower electrode and the projection, and an upper electrode is formed on the capacitor film.

Semiconductor device having projection on lower electrode and method for forming the same

A semiconductor device includes a lower electrode provided on a semiconductor substrate, an upper electrode provided on the lower electrode to overlap a part of the lower electrode, a first insulating film provided between the lower electrode and the upper electrode, and a second insulating film provided in contact with an upper part of the upper electrode and on the upper part of the lower electrode, and having a density higher than that of the first insulating film, the second insulating film covering a side surface and a top surface of the upper electrode.

Semiconductor device including capacitor including upper electrode covered with high density insulation film and production method thereof

A semiconductor deviceincludes an interconnect, a conductive layer(first conductive layer), an insulating layer(first insulating layer), another conductive layer(second conductive layer), another insulating layer(second insulating layer), a via plug(first via plug), and another via plug(second via plug). In the semiconductor device, the conductive layer, the insulating layerand the conductive layerconstitute a MIM capacitor (capacitor element). To be more detailed, the conductive layer, the insulating layerand the conductive layerserve as a lower electrode, an insulating capacitor film and an upper electrode, respectively. The insulating layercovers both the conductive layerand the interconnect. The insulating layerworks as the etching stopper for the via plugs

Growing community of inventors

Kanagawa, Japan

Takuji Onuma