Renesas Technology Corp.

Mitsubishi Denki Kabushiki Kaisha

Genusion, Inc.

Renesas Electronics Corporation

Toyo Suisan Kaisha, Ltd.

Taku Ogura

Tadaaki Yamauchi

Takashi Kubo

Hidenori Mitani

Natsuo Ajika

Kengo Aritomi

Kiyohiro Furutani

Satoshi Shimizu

Masaaki Mihara

Shoji Shukuri

Shigehiro Kuge

Satoshi Kawasaki

Minoru Senda

Yoshiki Kawajiri

Fumihiko Nitta

Yasuhiro Kashiwazaki

Takashi Itoh

Masafumi Yamakoshi

Junya Kanayama

Hisashi Sugiyama

Takeshi Hamamoto

Kazuo Kobayashi

Shinichi Kobayashi

Atsushi Ohba

Tomoshi Futatsuya

Takashi Hayasaka

Natsuo Aiika

Shoii Shukuri

Tsuyoshi Honma

A dried noodle having a porosity in a cross-sectional area of the noodle of from 0.1 to 15%, a unit porosity in the cross-sectional area of the noodle of from 0.01 to 1%, a gelatinization degree of 30 to 75% and a porous structure, the dried noodle being produced by a process including (a) preparing a noodle dough comprising a main raw material, water and a powder oil, which is entirely derived from an oil, in an amount of more than 0.5% by weight and less than 6% by weight with respect to a total weight of the main raw material, (b) forming a raw noodle body from the noodle dough, and (c) subjecting the raw noodle body to an airflow at a temperature of 90 to 150&#xb0; C. to evaporate the water, thereby foaming, drying and gelatinizing the raw noodle body, wherein the entire process does not include steaming.

Dried noodle

Provided is a dried noodle having a porosity in the cross-sectional area of the noodle of from 0.1 to 15%, a unit porosity in the cross-sectional area of the noodle of from 0.01 to 1%, a gelatinization degree of 30 to 75% and a porous structure.

Dried noodle and process for producing the same

A nonvolatile semiconductor memory device is provided which includes: a P-type memory cell transistor having a source, a drain, a gate, and a charge storage layer; and a control circuit which, in a case where the P-type memory cell transistor has its threshold greater than or equal to a first value (Vr) and less than or equal to a second value (Vrd), carries out a program operation of injecting electrons into the charge storage layer.

Read disturb control in a nonvolatile semiconductor memory device having P-type memory cell transistor

According to an aspect of the present invention, it is provided: a nonvolatile semiconductor memory device comprising: a plurality of bit lines arranged in a first direction; a plurality of source lines arranged in the first direction, the plurality of source lines being parallel to the plurality of bit lines, the plurality of source lines being distinct from the plurality of bit lines; a plurality of memory gate lines arranged in a second direction perpendicular to the first direction; a plurality of memory cells arranged in a matrix, each of the plurality of memory cells including a p type MIS nonvolatile transistor having a first terminal, a second terminal, a channel between the first terminal and the second terminal, a gate insulation film formed on the channel, a gate electrode connected to one corresponding memory gate line of the plurality of memory gate lines, and a carrier storage layer formed between the gate insulation film and the gate electrode, the first terminal being connected to one corresponding bit line of the plurality of bit lines and the second terminal being connected to one corresponding source line of the plurality of source lines.

Nonvolatile semiconductor memory device

A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.

Non-volatile semiconductor memory device and manufacturing method thereof

A semiconductor device includes a semiconductor substrate having first and second edge lines, address pads along the first edge line, and memory mats, each including normal memory blocks and a spare memory block. Each normal memory block has nonvolatile memory cells and is a unit of batch erase. The memory mats are arranged in a U-shaped area having a hollow portion facing the second edge line. The device includes column decoders arranged correspondingly to the memory mats, an analog/logic circuit arranged in the hollow portion, and a power supply pad arranged between the analog/logic circuit and the second edge line. The analog/logic circuit includes a charge pump circuit. The device further includes a first power supply interconnection supplying power supply voltage to the charge pump circuit from the power supply pad, and a second power supply interconnection supplying power supply voltage to the column decoder from the power supply pad.

Semiconductor memory device having memory block configuration

A memory apparatus includes a control circuit, a plurality of memory arrays, each of which contains a plurality of memory cells, and a current detecting circuit. The current detecting circuit measures a quantity of a current of a first memory array. A redundancy information is changed when the quantity of the current of the first memory array is over a first current quantity detected by the current detecting circuit. The control circuit controls an access to the memory arrays, and changes the access to the first memory array to a second memory array in accordance with the redundancy information.

Non-volatile semiconductor memory device

According to an one aspect of the present invention, it is provided a non-volatile semiconductor memory device comprising: a first N type well; a plurality of P type non-volatile memory cells arranged in matrix and formed in the N type well; a plurality of sub-bit lines, each of the sub-bit lines being connected to drains of the P type non-volatile memory cells in a respective one of columns of the matrix; a first P type well; and a plurality of N type selection transistors, each of the selection transistors selectively connecting a respective one of sub-bit lines to a corresponding one of main bit lines.

Non-volatile semiconductor memory device comprising capacitive coupling program inhibit circuitry

A transistor is arranged for electrically isolating a sense amplifier formed of a thin film transistor from a data line electrically coupled to the sense amplifier. When a write driver drives the data line, a control signal is applied to isolate the data line from the sense amplifier.

Nonvolatile memory device including circuit formed of thin film transistors

A nonvolatile semiconductor memory device includes a first PMOS transistor and a second PMOS transistor having a gate, the first and the second PMOS transistors being connected in series; and a first NMOS transistor and a second NMOS transistor having a gate, the first and the second NMOS transistors being connected in series; wherein the gate of the second PMOS transistor and the gate of the second NMOS transistor are commonly connected and floated.

Nonvolatile semiconductor memory device and usage method thereof

A memory array including memory mats is arranged in a U shape when seen in two dimensions, and a logic circuit and an analog circuit are arranged in a region unoccupied by the memory array. This facilitates transmission of power supply voltage and signals between the peripheral circuit including the analog and logic circuits and the pad band including power supply and data pads. The analog circuit is positioned close to the power supply pad, so that voltage drop due to the resistance of power supply interconnection is restricted. It is also possible to separate a charge pumping power supply interconnection and a peripheral circuit power supply interconnection in the vicinity of the power supply pad.

An object of this invention is to provide a rewritable nonvolatile memory cell that can have a wide reading margin, and can control both a word line and a bit line by changing the level of Vcc. As a solution, a flip-flop is formed by cross (loop) connect of inverters including memory transistors that can control a threshold voltage by charge injection into the side spacer of the transistors. In the case of writing data to one memory transistor, a high voltage is supplied to a source of the memory transistor through a source line and a high voltage is supplied to a gate of the memory transistor through a load transistor of the other side inverter. In the case of erasing the written data, a high voltage is supplied to the source of the memory transistor through the source line.

Nonvolatile semiconductor memory using an adjustable threshold voltage transistor in a flip-flop

An internal voltage generating circuit generates and supplies a boosted voltage higher than an internal power supply voltage, as an operating power supply voltage, to a sense amplifier in a read circuit for reading data of a memory cell. A bit line precharge current supplied via an internal data line is produced from the internal power supply voltage. It is possible to provide a nonvolatile semiconductor memory device, which can perform a precise sense operation and an accurate reading of data even under a low power supply voltage condition.

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Hyogo, Japan

Taku Ogura