Hitachi, Ltd.

Hitachi Denshi Kabushiki Kaisha

Takeyuki Endoh

Shigeru Yabuuchi

Kunihiro Okada

Kazuyuki Kodama

Jushi Ide

Norio Yokozawa

Yasutaka Shibuya

Kouichi Tanaka

Yoshiharu Itatsuda

In order to deliver an input signal of each operation cycle after a desired time delay, there are disposed data memory means for storing the input signal, counter means for appointing write addresses of the data memory means, and address memory means for appointing read addresses of the data memory means. The address memory means is divided into partial memory areas equal in number to time delay elements, whereupon while sampling the input signal at a predetermined sampling period and changing the count value of the counter means one by one for each of the desired time delay elements at each sampling point, the variations of the input signal in a sampling interval between the particular sampling point and the adjacent sampling point are successively written into the memory means. Further, while changing the contents of the partial memory areas corresponding to the desired time delay element to the number of the time delay elements in each sampling interval, the variations in a sampling interval preceding a predetermined sampling number to the particular sampling interval are successively read out from the memory means. The input signal of each operation cycle in the preceding sampling interval is presumed by an interpolation operation based on the variation and the sampling period, and the result is used as an output signal of the desired time delay element.

Method of generating time delay

A method of operation of a digital differential analyzer for performing the operation: ##EQU1## where Y is an integrand, .DELTA.Y is an increment of an input variable, R is a residue of the integrated value of the integrand, .DELTA.X is an increment of an independent variable, .DELTA.Z is an output increment of the integrated value of the integrand, K is a constant and n is an input number (a positive integer), in the ith iteration, uses a first mantissa M.sub.1, a second mantissa M.sub.2, a first exponent E.sub.1 and a second exponent E.sub.2 for expressing the abovementioned equation as follows, ##EQU2## then adjusts the radix points of the first and second mantissae in the bit number corresponding to the difference between the first and second exponents to adjust the mantissa portion to the greater exponent of the two, and thereafter calculates the mantissa portion to perform the abovementioned arithmetical operation and to obtain .DELTA.Z and R; the improvement wherein the mantissa portion of .DELTA.Z is expressed in terms of m (.gtoreq.2) bits by adding the most-significant bit corresponding to the first bit above the radix point to bits below the radix point and the radix point is then adjusted in accordance with the result of addition in order to obtain .DELTA.Z and R in accordance with the quantity of the result of addition for each iteration.

Arithmetical method for digital differential analyzer

A figure displaying device for generating a brightness signal which corresponds to a figure information to be displayed as well as for generating a brightness modulation signal which varies within a predetermined first region on a display screen. The device also generates a frequency characteristic control signal which varies within a predetermined second region on the display screen. Furthermore, the display is able to subject the brightness signal to a brightness modulation in accordance with the signal from the modulator generator with the brightness signal being controlled by the frequency characteristics control signal. The resultant figure displayed on a monitor is based on a modulation signal obtained through the modulation generator and the frequency characteristics control generator.

Figure displaying device

A colored display system for displaying a plurality of colored solid surfaces each of which is obtained by coloring or painting in a region, comprising circuit means for generating figure information signals representative of the respective solid surfaces, a priority circuit for selecting one of the figure information signals in response to a predetermined priority order when the figure information signals are simultaneously generated, a memory circuit for storing color information, circuit means for reading out the color information corresponding to the selected figure information signal from the memory circuit and a color cathode ray tube for displaying the colored solid surfaces in response to the color information read out.

Colored display system for displaying colored planar figures

A digital differential analyzer comprises an arithmetic unit for performing an integration operation, a control unit for controlling the arithmetic unit, a plurality of temporary storage means in the arithmetic unit for temporarily storing interim results of the arithmetic operation therein to relieve the influence of propagation delay time of the arithmetic unit.

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Tokyo, Japan

Takeyuki Endoh