Fuji Electric Co., Ltd.

Fuji Electric Device Technology Co., Ltd.

Fuji Electric Systems Co. Ltd.

Takeyoshi Nishimura

Tatsuhiko Fujihira

Takashi Kobayashi

Yasushi Niimura

Isamu Sugai

Takumi Fujimoto

Hidenori Takahashi

Masanori Inoue

Shuhei Tatemichi

Sota Watanabe

Takamasa Wakabayashi

Yasuhiko Onishi

Hitoshi Sumida

Toshiaki Sakata

Akihiko Ohi

Hiroyuki Tanaka

Kin-On Sin

Chun-Wai Ng

Yoshiaki Toyada

Hitoshi Abe

Seiji Momota

Tadanori Yamada

Makoto Shimosawa

Kazuya Yamaguchi

Ryo Maeta

Kazutoshi Sugimura

Toshihiro Arai

Shun Yamaguchi

Masao Yoshino

A method of manufacturing a silicon carbide semiconductor device includes selectively forming a semiconductor region of a conductivity type at a first main surface of a semiconductor substrate containing silicon carbide; forming a nickel layer above the semiconductor region; ion-implanting aluminum in the nickel layer; performing a heat treatment to the nickel layer implanted with the aluminum to thereby form an ohmic contact layer in ohmic contact with the semiconductor region; forming a first electrode that is in contact with the ohmic contact layer, the semiconductor region, and the semiconductor substrate; and forming a second electrode on a second main surface of the semiconductor substrate.

Method of manufacturing silicon carbide semiconductor device and silicon carbide semiconductor device

Provided is a semiconductor device including: a drift region of first conductivity type provided in a semiconductor substrate; a base region of second conductivity type provided in the semiconductor substrate; an emitter region of first conductivity type provided at a front surface of the semiconductor substrate; a contact region of second conductivity type provided on the base region and having a higher doping concentration than the base region; a contact trench portion provided at the front surface of the semiconductor substrate; a first barrier layer provided at a side wall and a bottom surface of the contact trench portion; and a second barrier layer provided in contact with the contact region at the side wall of the contact trench portion.

Semiconductor device

Provided are a semiconductor element and a semiconductor device capable of achieving on-resistance reduction and miniaturization. The semiconductor element is used in a semiconductor switch for protecting an electric circuit, and includes a semiconductor substrate SB, a MOS transistor Tr provided on the semiconductor substrate SB, and a source electrode SE provided on a front surfaceside of the semiconductor substrate SB. The MOS transistor Tr includes an n-type source regionconnected to the source electrode SE, an n-type drift regionarranged away from the source region, and a p-type well regionarranged between the source regionand the drift region. The source regionis interposed between the source electrode SE and the well region

Semiconductor element and semiconductor device

A semiconductor device includes a semiconductor element having a surface electrode layer; a first wire that is electrically connected to the first main surface of the surface electrode layer at a plurality of first connecting portions and is arranged in a first direction on the first main surface; and a second wire that is electrically connected to the first main surface of the surface electrode layer at a second connecting portion and is arranged in a second direction on the first main surface, wherein a second circle equivalent diameter, which is a diameter of a circle having a same cross-sectional area as the second wire, is larger than a first circle equivalent diameter, which is a diameter of a circle having a same cross-sectional area as the first wire.

Semiconductor device and method for manufacturing semiconductor device having first and second wires in different diameter

A semiconductor device has an active region through which current passes and an edge termination structure region. On a front surface of a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type is provided. On a surface of the first semiconductor layer, a parallel pn structure including first columns of the first conductivity type and second columns of a second conductivity type disposed to repeatedly alternate one another is provided. The second columns in the active region include first regions and second regions. A distance from the front surface of the semiconductor substrate to a bottom surface of one of the first regions is greater than a distance from the front surface of the semiconductor substrate to a bottom surface of one of the second regions.

Superjunction semiconductor device having parallel PN structure with column structure and method of manufacturing the same

A semiconductor device, including a parallel pn layer formed on a semiconductor substrate, and an insulated gate structure provided on the parallel pn layer. The parallel pn layer includes a plurality of first regions and a plurality of second regions disposed repeatedly alternating one another along a first direction that is parallel to an upper surface of the semiconductor substrate. Each of the first regions and second regions has, along the first direction, an impurity concentration that has a maximum value thereof at a peak position and that decreases gradually from the peak position. Each of the first regions and second regions has, along a depth direction thereof, a first part and a second part, a gradient of the impurity concentration along the first direction being respectively symmetrical and asymmetrical in the first part and in the second part, with respect to the peak position.

A semiconductor device includes an enhancement mode MOSFET and a junction FET. The MOSFET has a first semiconductor substrate of a first conductivity type, a first first-semiconductor-layer of the first conductivity type, first second-semiconductor-regions of a second conductivity type, first first-semiconductor-regions of the first conductivity type, first gate insulating films, first gate electrodes, a first first-electrode, and a first second-electrode. The FET has a second semiconductor substrate of the first conductivity type, a second first-semiconductor-layer of the first conductivity type, second first-semiconductor-regions of the first conductivity type, a second second-semiconductor-layer of the second conductivity type, second gate electrodes, a second first-electrode, and a second second-electrode. The first second-electrode and the second second-electrode are connected electrically.

A semiconductor layer may be subjected to etching to form a trench therein. An epitaxial layer may be further formed in the trench. Here, the impurity concentration of the epitaxial layer is controlled to be lower than that of the semiconductor layer. In this manner, concentration of electrical fields in the trench is reduced. A first innovations herein provides a semiconductor device including a first semiconductor layer containing impurities of a first conductivity type, a trench provided in the first semiconductor layer on a front surface side thereof, and a second semiconductor layer provided on an inner wall of the trench, where the second semiconductor layer contains impurities of the first conductivity type at a lower concentration than the first semiconductor layer.

Semiconductor device and method of manufacturing semiconductor device

Provided are a semiconductor element and a semiconductor device capable of reducing possibilities of malfunctions and breakdowns due to temperature rise. A semiconductor element () includes a first MOS transistor (Tr), a second MOS transistor (Tr), and a temperature detecting element (TD) that are provided on a semiconductor substrate (SB). The first MOS transistor (Tr) includes an n-type source region (), an n-type first semiconductor region () arranged away from the source region () and a p-type well region () arranged between the source region () and the first semiconductor region (). The second MOS transistor (Tr) includes an n-type source region () an n-type second semiconductor region () arranged away from the source region (), and a p-type well region () arranged between the source region () and the second semiconductor region (). The first semiconductor region () is connected to the second semiconductor region ().

In each n-type epitaxial layer, p-type impurity regions are respectively formed by performing for each stacking of an n-type epitaxial layer, ion implantation using a resist mask. In a first n-type epitaxial layer, a p-type impurity region is formed at an inner wall of an impurity diffusion trench formed by dry etching. In a second and third n-type epitaxial layer, p-type impurity regions are formed respectively at an inner wall of impurity diffusion trenches that are recesses respectively corresponding to the impurity diffusion trenches of the first and the second n-type epitaxial layers respectively therebelow. The resist mask has an opening width that is wider than widths of open ends of the impurity diffusion trenches. The p-type impurity regions are connected by thermal diffusion processing, thereby forming a parallel pn layer constituted by p-type regions having a high aspect ratio and n-type regions respectively between the p-type regions.

Method of manufacturing semiconductor device

A current limiting resistor opposes a p-type anode region of a bootstrap diode in a depth direction, across an insulating film. The current limiting resistor is configured by poly-silicon layers constituting poly-silicon resistors, and a poly-silicon connector that is a connector connected to a limiting resistor electrode. The poly-silicon layers are disposed further outside than is the poly-silicon connector and each has a first end connected to the poly-silicon connector. The poly-silicon layers each have a second end and a part that is toward the second end and that is in contact with an anode electrode via a contact hole. Further, the poly-silicon layers are disposed evenly between a part thereof connected to the poly-silicon connector and the contact hole.

An n-type region and a p-type region of a first parallel pn layer are arranged parallel to a base front surface, in a striped planar layout extending from an active region over an edge termination region. In the n-type region, a gate trench extending linearly along a first direction is provided. In an intermediate region, in a surface region on the base front surface side of the first parallel pn layer, a second parallel pn layer is provided. The second parallel pn layer is arranged having a repetition cycle shifted along a second direction &#xbd; a cell with respect to a repetition cycle of the n-type region and the p-type region of the first parallel pn layer. A gate trench termination portion terminates in the intermediate region between the active region and the edge termination region, and is covered by the p-type region of the second parallel pn layer.

A front surface electrode common to a plurality of unit cells is provided substantially all over an active region of a semiconductor element. A plurality of electrode pads on the front surface electrode are closer to the outer peripheral portion side than the central portion of the active region. Different wires are joined to substantially the center of each electrode pad. The active region is divided into two or more segments so that the segments are aligned along the path of current flowing through the front surface electrode, and unit cells different in conduction ability are disposed respectively in each segment. Unit cells lowest in conduction ability are in the first segment farthest from junctions of the wires and electrode pads, and the unit cells are disposed so that the farther apart from the junctions of the wires and electrode pads, the lower in conduction ability the unit cells are.

A capacitive component region is formed below a temperature detecting diode or below a protective diode. In addition, the capacitive component region is formed below an anode metal wiring line connecting the temperature detecting diode and an anode electrode pad and below a cathode metal wiring line connecting the temperature detecting diode and a cathode electrode pad. The capacitive component region is an insulating film interposed between polysilicon layers. Specifically, a first insulating film, a polysilicon conductive layer, and a second insulating film are sequentially formed on a first main surface of a semiconductor substrate, and the temperature detecting diode, the protective diode, the anode metal wiring line, or the cathode metal wiring line is formed on the upper surface of the second insulating film. Therefore, it is possible to improve the static electricity resistance of the temperature detecting diode or the protective diode.

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Matsumoto, Japan

Takeyoshi Nishimura