Mitsubishi Denki Kabushiki Kaisha

Takesi Inoue

Atsuo Yamaguchi

Shuzo Fujioka

Kenichi Takahira

Toshiyuki Matsubara

Shigeru Furuta

A noncontacting card containing a coil circuit has at least two spiral windings connected in parallel for electromagnetically coupling the card to a terminal and a processing circuit connected to the coil circuit for signal processing. A terminal for a noncontacting card including a coil circuit has at least two spiral windings connected in parallel for electromagnetically coupling the terminal to a noncontacting card and a processing circuit connected to the coil circuit for signal processing. A noncontacting transmission system includes a noncontacting card having a coil circuit including at least two spiral windings connected in parallel and a terminal having a coil circuit including at least two spiral winding connected in parallel, the coil circuits of the noncontacting card and the terminal being electromagnetically coupled for transmitting electrical power to the noncontacting card and exchanging data between the terminal and the noncontacting card.

Noncontacting card, noncontacting-card terminal and noncontacting

A non-contact IC card for receiving electrical power from and exchanging signals with a terminal device without contact has a power consuming circuit which consumes electrical power when the electrical power consumption in the IC card is small. The rate of power consumption by the power consuming circuit is controllable in accordance with the state of the IC card, such as a stand-by state, receiving state, transmitting state, and signal processing state. The power consuming circuit includes a series connection of a switching element and a resistor connected between high-voltage and grounding terminals. The state of the switching element is sequentially controlled by a microcomputer. The control of the power consumption is attained by selecting one of a plurality of the power consuming circuits having different resistance values.

Non-contact IC card

A memory system storing data detects and corrects an error in the stored data. The memory device includes a coding circuit for generating a systematic code including a data word and an error checking and correcting (ECC) code when the data word is supplied from a data bus during data writing, a memory cell array for storing the systematic code, and a sense amplifier for reading the systematic code from the memory cell. An error checking and correcting system generates a syndrome from the systematic code, decodes the syndrome to determine whether an error exists, identifies a bit position at which an error has occurred, and corrects the error contained in the data word by inverting a bit of the data word in the position at which the error has occured. The system includes a multiplexer for outputting the corrected data word to the data bus and a code reading circuit, for example, an ECC code register, for reading the ECC code generated by the coding circuit directly into the data bus. With this arrangement, it is possible to immediately and independently check the function of the coding circuit without influence from the memory cell array.

Memory device

A microcomputer comprises EEPROM provided as a fixed storage unit and a CPU for controlling the operation of the EEPROM, in which the EEPROM contains a divider which divides a stable clock signal from the outside of the microcomputer and converts it to a clock signal with a desired frequency, the clock signal is used as a synchronizing signal necessary for the writing data into the EEPROM. The CPU controls the operation of the EEPROM and sets the dividing ratio of the divider contained in the EEPROM at a desired value in accordance with the assignment from the outside of the microcomputer.

Microcomputer

A microprocessor system including an EEPROM with a page mode writing function that prevents writing of erroneous data. The circuit includes a memory cell array divided into a plurality of pages each having a predetermined number of bytes, a data latch for latching bytes corresponding to a page, an exterior write control circuit which enables the data latch in response to a signal from the CPU to latch a sequence of bytes corresponding to a page, and an interior write control circuit which enables the memory cell array so that the bytes latched in the data latch are transferred therefrom to a page of the memory cell array. The exterior write control circuit includes a time measurement circuit and an interior write suppression circuit. The time measurement circuit measures the time which elapses from the initiation of the latching of bytes into the data latch, and outputs an overflow signal when the measured time exceeds a predetermined limit. The interior write suppression circuit suppresses the interior write control circuit, in response to the overflow signal, so that the transfer of erroneous data bytes from the data latch to a page of the memory cell array is prevented.

Microprocessor having miswriting preventing function

An IC card includes an addressable CPU having a memory space including a special area including a first plurality of memory addresses which are addressable with a short instruction word, first and second memories in which test and application programs are stored, respectively, a bus which connects the CPU and the first and second memories, a first selection circuit for forming a first memory mapping arrangement in which at least a portion of the first memory is superimposed on the special area, a second selection circuit for forming a second memory mapping arrangement in which at least a portion of the second memory is superimposed on the special area, a detection circuit for detecting the execution of the test program or the application program, and a changeover circuit arranged to selectively operate the first and second selection circuits according to the result of detection executed by the detection circuit. The above-described arrangement makes it possible to effectively use the special area to efficiently execute either the application program or the test program.

IC card

An IC card has a CPU, a first memory for storing a test program, a second memory for storing an application progam, a bus connecting the CPU and the first and second memories. A detection circuit for detecting whether the CPU has began executing the application program stored in the second memory, and a disconnection circuit for disconnecting the first memory from the bus when the detection circuit detects that the CPU has begun executing the application program. The above-described arrangement makes it impossible to access the test program in the system ROM from the application program thereby preventing the occurrence of incorrect access.

IC card having system ROM selection inhibit

A system for noncontact transfer of information between an IC card and a card reader/writer, wherein the IC card and the card reader/writer each comprises an IC chip having a logic circuit and at least one electromagnetically inductive coil for transfer of information integrated therein. A power supply is located at least partly on the IC card for providing power to the IC chip of the IC card.

Noncontact type IC card and system for noncontact transfer of

A memory device for detecting and correcting errors in stored data includes a circuit for generating an error-detection/correction code with respect to data to be stored, a memory cell array in which the data and the error-detection/correction code are stored, an error-detection/correction circuit for detecting and corrrecting errors in the data by using the error-detection/correction code when the data is read out of the memory cell array, and a function test circuit selectively and directly connected to the error-detection/correction circuit for testing the error-detection/correction circuit.

Memory with function test of error detection/correction device

An IC module having a circuit board with obverse and reverse sides on which IC chips are mounted. This IC module is provided with at least one pair of IC chips having inverted operating circuit patterns and mounted back-to-back on the obverse and reverse sides of the circuit board at desired positions such that the inverted operating circuit pattern of one chip coincides with that of the other as seen through the circuit board, at least one printed circuit board pattern corresponding to one of the operating circuit patterns and formed on one of the obverse or reverse sides of the circuit board and used in common for the pairs of IC chips, wire-bonding pads formed around the peripheries of each of the pair of IC chips to connect the circuit board pattern to the terminals of the pair of IC chips, at least one board through hole for connecting the wire-bonding pads on one side of the circuit board to the other, and a pair of selecting signal lines provided for the pair of IC chips. Further, it is possible to form independent or separated circuit board patterns which are for different objects on both the obverse and reverse sides of the circuit board, respectively, and use them in common for both sides thereof.

Growing community of inventors

Itami, Japan

Takesi Inoue