Matsushita Electric Works, Ltd.

Takeshi Yoshida

Yuji Suzuki

Yoshiki Hayasaki

Hitomichi Takano

Masahiko Suzumura

Takashi Kishida

Yoshifumi Shirai

Yasunori Miyamoto

Takaaki Yoshihara

A solid state relay composed of a series connected pair of LDMOSFETs has a minimized output capacitance. Each LDMOSFET is configured to have a silicon layer of a first conductive type, a drain region of the first conductive type diffused in the top surface of the silicon layer, a well region of a second conductive type diffused in the silicon layer in a laterally spaced relation from the drain region, and a source region of the first conductive type diffused within the well region to define a channel extending between the source region and a confronting edge of the well region along the top surface of the silicon layer. Each LDMOSFET is of an SOI (Silicon-On-Insulator) structure composed of a silicon substrate placed on a supporting plate, a buried oxide layer on the silicon substrate, and the silicon layer on the buried oxide layer. The well region is diffused over the full depth of the silicon layer to have its bottom in contact with the buried oxide layer, so that the well region forms with the silicon layer a P-N interface only at a small area adjacent the channel. Because of this reduced P-N interface and also because of the buried oxide layer exhibiting a much lower inductive capacitance than the silicon layer, it is possible to greatly reduce a drain-source capacitance for minimizing the output capacitance of the relay in the non-conductive condition.

Solid-state relay

To provide a semiconductor device having a large allowable current, a demanded withstand voltage, and small output capacitance and resistance, the semiconductor device comprises a semiconductor layer formed on a semiconductor substrate, and the semiconductor layer includes a first conductivity type-drain region, a second conductivity type-well region apart from the drain region, a first conductivity type-source region in the well region apart from one end of the well region on the side of the drain region, a first conductivity type-drift region formed between one end of the well region and the drain region and in contact with the well region and the drain region, respectively, and a gate electrode formed spaced a gate oxide layer and on the well region located between the drift region and the source region; and the impurity concentration of the drift region decreases in the lateral direction and also in the vertical direction, respectively, as the distance from the drain region increases.

Semiconductor device and process for producing the same

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Shijonawate, Japan

Takeshi Yoshida