Adv Antest Corporation

Takeshi Yaguchi

Takahiro Nakajima

Hajime Sugimura

Mamoru Hiraide

Toshiaki Adachi

Hideyuki Oshima

Tetsuya Koishi

Shintaro Ichikai

Tadashi Morita

A waveform data acquisition module acquires the waveforms of electrical signals for multiple channels. A memory controller continuously writes a digital signal Sto one from among a first memory unit and a second memory unit. When a given memory unit has become full, the memory controller notifies an external higher-level controller that the corresponding memory unit is full and switches the wiring target to the other memory unit.

Test apparatus

In order to efficiently test a plurality of types of devices under test, provided is a test apparatus that tests a device under test, comprising one or more test modules that each include a plurality of testing sections testing the device under test by exchanging signals with the device under test; and a plurality of control apparatuses that control operation of the testing sections. In each of the one or more test modules, the plurality of testing sections are each allocated to one of the plurality of control apparatuses, and each of the control apparatuses is capable of executing a test program managed by a different user, and controls operation of the testing sections allocated thereto.

Test apparatus and test module

A test apparatus that tests a device under test, comprising a control apparatus sequentially executing a plurality of test programs and controlling testing of the device under test; and a test module controlled by the control apparatus to test the device under test by communicating with the device under test and to transmit a test result of each test program to the control apparatus. The test module includes memories that store the test results of the test programs, and starts a subsequent test such that at least a portion of a result processing time period of a current test, from when a test result stored in a first memory begins being transmitted to the control apparatus to when processing of the test result by the control apparatus ends, overlaps with at least a portion of a test execution period in which the subsequent test is executed using a second memory.

Provided is a test apparatus that tests a device under test, comprising a test module that communicates with the device under test to test the device under test; and a control apparatus that executes a plurality of test programs, causes the test module to perform tests corresponding respectively to the test programs, receives test results from the test module, and performs predetermined result processes on the test results. The control apparatus stores an execution order of the test programs, and executes at least a portion of the result processes in an order indicated by the stored execution order.

Provided is a test apparatus for testing at least one device under test, including: a test module that includes a plurality of test sections, the plurality of test sections testing the device under test by exchanging signals with the device under test; and a plurality of test control sections that control the plurality of test sections, where the test module includes the plurality of test sections; a setting storage section that stores setting as to which of the plurality of test control sections should be associated with each of the plurality of test sections; and an interface section that is connected to the plurality of test sections, provides an access request issued from one of the plurality of test control sections and directed to the test module, to a test section associated with the test control section, and is able to set, independently for each of the plurality of test sections, which of the plurality of test control sections should control the test section.

Provided is a test apparatus for testing a device under test, including: a plurality of test modules that exchange signals with the device under test; a bus to which the plurality of test modules are connected; and a test control section that controls the plurality of test modules via the bus, where each of the plurality of test modules includes: a test section that exchanges signals with the device under test, and a module control section that controls the test section, and the module control section of each test module exchanges signals with the module control section of another test module, via the bus.

Test apparatus and test method

Provided is a test apparatus and a test method related to the test apparatus for testing a device under test, including: a plurality of test modules that exchange a signal with the device under test; a test control section that outputs a group read instruction for collectively reading data stored in two or more of the test modules; and a control interface section that reads the data from the two or more test modules according to the group read instruction, and collectively sends the read data to the test control section.

A test apparatus for testing an electric device includes a plurality of signal input-output units for inputting and/or outputting test signals in response to each of a plurality of terminals included by the electric device, a channel selection memory for storing pieces of channel selection information indicating whether each of the signal input-output units should perform setting based on a setting condition or not, a setting condition memory for storing the setting condition with regard to the signal input-output unit, and a controlling means for retrieving and supplying the setting condition stored in the setting condition memory and the channel selection information stored in the channel selection memory to the signal input-output units based on a setting instruction, when receiving the setting instruction to set the setting condition of the signal input-output unit, wherein when at least one of the signal input-output units is selected by the channel selection information supplied from the controlling means, the one of the signal input-output units is set based on the setting condition supplied from the controlling means.

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Saitama, Japan

Takeshi Yaguchi