Hitachi, Ltd.

Other

Renesas Technology Corp.

Trio Kabushiki Kaisha

Hitachi Ulsi Engineering Corp.

Hitachi Engineering Co., Ltd.

Hitachi Keiyo Engineering Co., Ltd.

Hitachi Ulsi Systems Co., Ltd.

Hitachi Vlsi Engineering Corp.

Hitachi-high-technologies Corporation

Hitachi Vsli Engineering Corp.

Hitachi Ulsi

Takeshi Wada

Hitoshi Kume

Tadashi Muto

Koichi Seki

Kazuyoshi Shoji

Yasurou Kubota

Kunihiro Katayama

Takashi Totsuka

Takashi Tsunehiro

Takeshi Suzuki

Kenichi Kaki

Jun Kitahara

Hajime Yamagami

Tsunehiro Tobita

Yukihiko Miyamoto

Ryuichi Hattori

Yukihiro Seki

Takashi Kikuchi

Takao Okubo

Tsuneo Yamada

Masamichi Kishi

Shigeru Kadowaki

Manabu Saito

Yosio Takaya

Masanori Ienaka

Yasuo Kominami

Akinori Matsuo

Yasuhiro Nakamura

Masashi Watanabe

Hisanao Kita

Tetsuo Okuni

Masashi Wada

Toshihiro Tanaka

Satoshi Meguro

Hideaki Yamamoto

Kazuhiro Komori

Toshihisa Tsukada

Tetsuo Adachi

Tadanobu Toba

Toshiaki Nishimoto

Hideyuki Aoki

Takaaki Hagiwara

Susumu Hatano

Yasushi Takahashi

Yuji Wada

Masayasu Kawamura

Shuji Kikuchi

Katsunori Hirano

Kiyofumi Uchibori

Masaaki Namba

Shin'ichi Ikenaga

Yoji Akutsu

Yuji Sonoda

Kouichi Seki

Noboru Umehara

Yoshinori Karatsu

Fujio Yamamoto

Kenji Nishimoto

Tatsuo Yonezawa

Jun Kitano

Masaaki Mochiduki

Toshiko Koizumi

Toshio Namatame

Noboru Uchida

Masao Ishihara

Shigeki Katsumi

Yoshio Namatame, Deceased

Hironori Kadowaki

Susumu Fujishima

Tatsuji Wada

Toshio Nemoto

Michihiro Mishima

Wada Masashi

A nonvolatile memory apparatus which includes plural memories one of which is a nonvolatile memory such as a Flash EEPROM capable of being specified a plurality of operations from a processing unit of the apparatus including an erase operation, the erase operation in the nonvolatile memory performs a threshold voltage moving operation and a verify operation, and the nonvolatile memory is capable of releasing the I/O bus during the erase operation to thereby allow accessing of other memories and/or system components. For example, during this erase operation, the Flash EEPROM is able to free the I/O data terminal such that the EEPROM becomes electrically isolated from the CPU. The CPU is then able to perform data processing by the system bus where information can then be transferred/received such as between other memories, e.g., ROM and RAM, and otherwise with the I/O port.

Nonvolatile memory apparatus having a processor and plural memories one or more of which is a nonvolatile memory having circuitry which performs an erase operation and an erase verify operation when the processor specifies the erase operation mode to the nonvolatile memory

A memory test system can screen objects of tests accurately at low cost in quasi-operating conditions by utilizing a personal computer (PC). The system utilizes a PC tester comprising a measurement PC unit that carries a memory module to be used as reference; a signal distribution unit for distributing the signal taken out form the measurement PC unit; a plurality of performance boards (PFBs) mounted with respective objected products to be observed simultaneously by using the signals distributed by the signal distribution unit; a display panel for displaying the current status of the test that is being conducted; a power source for producing the operating voltage of the system; and a control PC for controlling the selection of test parameters and various analytical operations. The PC tester is adapted to take out the signal from the chipset LSI (large scale integrated circuit) on the PC mother board in the measurement PC unit to the individual memories on the memory module or the memory module per se and test them in quasi-operating conditions.

Method and apparatus for testing a memory device in quasi-operating conditions

A signature circuit, i.e., a random-number generating circuit, is provided in a memory test apparatus. Also, a signature circuit is provided in each of devices-under-test. This configuration allows the large number of semiconductor integrated-circuit devices to be tested at one time with a high efficiency. This condition realizes a tremendous reduction in the test cost.

Semiconductor device, and the method of testing or making of the semiconductor device

Nonvolatile semiconductor memory device

An EEPROM having an erasing control circuit that performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the disclosure, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode.

A nonvolatile memory apparatus contains plural memories, at least one of which is a nonvolatile memory, and a processing unit. Data input/output (I/O) terminals of the memories and processing unit are mutually coupled by a bus. When the nonvolatile memory is brought into an erasing mode by the processing unit, it becomes electrically isolated as a result of freeing the connection of the I/O terminal thereof during the erase operation. Accordingly, the processing unit is capable of accessing other memories via the bus where information can then be transferred/received between other memory devices and, otherwise, with the input/output port of the system. Control by the processing unit requires a relatively short time during which the erasing commencement is instructed so as to minimize interruption of the throughput capability of the system. Following the designation of an erasing mode, a data polling mode is designated.

Nonvolatile semiconductor memory apparatus

A semiconductor file system features a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating correspondence between physical and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information. The controller determines a physical sector address. The control section is for controlling input/output of data from/to the external system and for temporarily storing write data into the first nonvolatile memory from the external system in the volatile memory and then transferring the write data from the volatile memory to the first nonvolatile memory.

Flash memory control method and apparatus processing system therewith

An electrically erasable semiconductor nonvolatile memory device has an array of memory cells arranged in rows and columns and one or more information erasure signal generating circuits. Each of the memory cells of the memory cell array includes a field-effect transistor element having a control gate connected with a word line conductor extending in a direction of the rows, a floating gate where carriers may be accumulated, a drain connected with a data line conductor extending in the direction of the columns and a source connected with a source conductor. The memory cell array may be divided into a plurality of memory blocks so as to have boundaries in the row direction or in the column direction, with the source conductors arranged in the row direction or in the column direction. Information erasure signals may be supplied to the source conductors or data line conductors with a time delay therebetween.

Electrically erasable semiconductor non-volatile memory device having memory cell array divided into memory blocks

A control method and system when a flash memory is used. as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data. The controller comprises control means for determining a physical sector address forming predetermined high-order bits of the physical address when data is output from the first nonvolatile memory or when data is input to the volatile memory, means for storing the determined physical sector address, and means for consecutively generating addresses in a sector determined by the physical sector address. The control section is responsive to the interface information, the first management information, and the second management information for controlling input/output of data from/to the external system and for temporarily storing write data into the first nonvolatile memory from the external system in the volatile memory and then transferring the write data from the volatile memory to the first nonvolatile memory. The consecutive address generation means and the sector address storage means output the physical sector address and the consecutively generated addresses to the first nonvolatile memory and the volatile memory when data at the physical sector address is output from the first nonvolatile memory or when data at the physical sector address is input to the volatile memory.

Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.

A control method and system when a flash memory is used as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data. The controller has a control means for determining a physical sector address forming predetermined high-order bits of the physical address when data is output from the first nonvolatile memory or when data is input to the volatile memory, means for storing the determined physical sector address, and means for consecutively generating addresses in a sector determined by the physical sector address.

Flash memory control method and information processing system therewith

Growing community of inventors

Akishima, Japan

Takeshi Wada