Fuji Electric Co., Ltd.

Mitsubishi Electric Corporation

Fuji Electric Device Technology Co., Ltd.

Takeshi Tawara

Hidekazu Tsuchida

Yasuyuki Kawada

Koichi Murata

Yoshiyuki Yonezawa

Tetsuya Miyazawa

Shinsuke Harada

Koji Nakayama

Shun-ichi Nakamura

Masahide Gotoh

Kensuke Takenaka

Akihiro Koyama

Akimasa Kinoshita

Manabu Takei

Yasunori Tanaka

Shinichiro Matsunaga

Tomohisa Kato

Tomonori Mizushima

Masaki Miyazato

Kazutoshi Kojima

Mina Ryo

Mitsuru Sometani

Akihiro Otsuki

Masaaki Miyajima

Tae Tawara

Mina Ohse

Kouichi Murata

Yuji Kiuchi

A silicon carbide semiconductor device has an active region and a termination structure portion disposed outside of the active region. The silicon carbide semiconductor device includes a semiconductor substrate of a second conductivity type, a first semiconductor layer of the second conductivity type, a second semiconductor layer of a first conductivity type, first semiconductor regions of the second conductivity type, second semiconductor regions of the first conductivity type, a gate insulating film, a gate electrode, a first electrode, and a second electrode. During bipolar operation, a smaller density among an electron density and a hole density of an end of the second semiconductor layer in the termination structure portion is at most 1×10/cm.

Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device

A method of manufacturing a superjunction silicon carbide semiconductor device is provided, enabling a reduction of the number of times a combination of epitaxial growth and ion implantation for forming a parallel pn structure is performed. In the method of manufacturing the superjunction silicon carbide semiconductor device, forming an epitaxial layerof a second conductivity type on a front surface of a silicon carbide semiconductor substrateof a first conductivity type and selectively forming semiconductor regionsof the first conductivity type by implanting nitrogen ions in the epitaxial layer are repeated multiple times, thereby forming the parallel pn structure.

Super junction silicon carbide semiconductor device and manufacturing method thereof

A vertical metal oxide semiconductor field effect transistor, including a starting substrate of a first conductivity type, a second first-conductivity-type epitaxial layer provided on a first surface of the starting substrate via a first first-conductivity-type epitaxial layer, a first semiconductor region of the first conductivity type provided as a portion of the second first-conductivity-type epitaxial layer, a second-conductivity-type epitaxial layer forming a pn junction interface with the second first-conductivity-type epitaxial layer and supplying a minority carrier to the second first-conductivity-type epitaxial layer, a plurality of second semiconductor regions of the first conductivity type selectively provided in the second-conductivity-type epitaxial layer, a plurality of trenches penetrating through the second semiconductor regions and the second-conductivity-type epitaxial layer, and a plurality of gate electrodes provided in the trenches via gate insulating films. A lifetime of the minority carrier of the first semiconductor region is shorter than that of the rest of the second first-conductivity-type epitaxial layer.

Vertical MOSFET having trench gate structure containing silicon carbide

A silicon carbide semiconductor device includes, sequentially, a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type provided on the first semiconductor layer, a third semiconductor layer of the first conductivity type provided on the second semiconductor layer, and a fourth semiconductor layer of a second conductivity type provided on the third semiconductor layer. A first electrode is provided on the first semiconductor layer, and a second electrode is provided on the fourth semiconductor layer. An impurity concentration of the second semiconductor layer is higher than that of the first semiconductor layer, and an impurity concentration of the third semiconductor layer is lower than that of the second semiconductor layer. The first semiconductor layer also contains, at a surface thereof in contact with the second semiconductor layer, a second impurity different from a first impurity that determines a conductivity type of the first semiconductor layer.

A silicon carbide epitaxial substrate including a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, and a high-density foreign element region. The first semiconductor layer is provided at a front surface of the silicon carbide semiconductor substrate and has an impurity concentration lower than that of the silicon carbide semiconductor substrate. The high-density foreign element region is provided in the silicon carbide semiconductor substrate at a predetermined depth from the front surface thereof. The high-density foreign element region contains an element other than carbon and silicon, at a density higher than that of the silicon carbide semiconductor substrate.

Silicon carbide epitaxial substrate, method of manufacturing thereof, silicon carbide semiconductor device, and method of manufacturing thereof

During epitaxial growth of an n-type drift layer having a uniform nitrogen concentration, vanadium is doped in addition to the nitrogen, whereby an n-type lifetime reduced layer is selectively formed in the n-type drift layer. The n-type lifetime reduced layer is disposed at a depth that is more than 5 &#x3bc;m from a pn junction surface between a p-type anode layer and the n-type drift layer in a direction toward a cathode side, and the n-type lifetime reduced layer is disposed separated from the pn junction surface. Further, the n-type lifetime reduced layer is disposed in a range from the pn junction surface to a depth that is &#x2153; times a thickness of the n-type drift layer. A vanadium concentration of the n-type lifetime reduced layer is 1/100 to &#x2155; of a nitrogen concentration of the n-type lifetime reduced layer.

Silicon carbide semiconductor device and a method of manufacturing the silicon carbide semiconductor device

A silicon carbide semiconductor substrate includes a silicon carbide substrate of a first conductivity type, an epitaxial layer of the first conductivity type provided on a front surface of the silicon carbide substrate, an impurity concentration of the epitaxial layer being 1&#xd7;10/cmto 1&#xd7;10/cm, and a film thickness of the epitaxial layer being 1 &#x3bc;m to 5 &#x3bc;m. The silicon carbide semiconductor substrate further includes a buffer layer of the first conductivity type provided on a surface of a first side of the epitaxial layer opposite a second side facing the silicon carbide substrate, an impurity concentration of the buffer layer being about a same as that of the silicon carbide substrate, and a drift layer of the first conductivity type provided on a surface of a first side of the buffer layer opposite a second side facing toward the silicon carbide substrate, an impurity concentration of the drift layer being lower than that of the buffer layer.

Silicon carbide semiconductor substrate, method of manufacturing silicon carbide semiconductor substrate, semiconductor device, and method of manufacturing semiconductor device

An n-type epitaxial layer is grown on a front surface of the silicon carbide substrate by a CVD method in a mixed gas atmosphere containing a source gas, a carrier gas, a doping gas, an additive gas, and a gas containing vanadium. The doping gas is nitrogen gas; and the gas containing vanadium is vanadium tetrachloride gas. In the mixed gas atmosphere, the vanadium bonds with the nitrogen, producing vanadium nitride, whereby the nitrogen concentration in the mixed gas atmosphere substantially decreases. As a result, the nitrogen taken in by the n-type epitaxial layer decreases and the n-type epitaxial layer including nitrogen and vanadium as dopants is grown having a low impurity concentration.

Silicon carbide semiconductor substrate, method of manufacturing a silicon carbide semiconductor device, and silicon carbide semiconductor device

On a front surface of an n-type starting substrate containing silicon carbide, a pin diode is configured having silicon carbide layers constituting an n-type buffer layer, an n-type drift layer, and a p-type anode layer sequentially formed by epitaxial growth. The n-type buffer layer is formed by so-called co-doping of nitrogen and vanadium, which forms a recombination center, together with an n-type impurity. The n-type buffer layer includes a first part disposed at a side of a second interface of the buffer layer with the substrate and a second part disposed at side of a first interface of the buffer layer with the drift layer. The vanadium concentration in the second part is lower than that in the first part. The vanadium concentration in the second part is at most one tenth of the maximum value Vmax of the vanadium concentration in the n-type buffer layer.

A silicon carbide semiconductor device, including a silicon carbide semiconductor substrate of a first conductivity type, a first silicon carbide semiconductor deposition layer of the first conductivity type, deposited on a front surface of the silicon carbide semiconductor substrate and having an impurity concentration that is lower than that of the silicon carbide semiconductor substrate, a base region of a second conductivity type, selectively provided in the first silicon carbide semiconductor deposition layer at a front surface thereof, and a second silicon carbide semiconductor deposition layer of the second conductivity type, deposited on the front surface of the first silicon carbide semiconductor deposition layer. The base region has an impurity concentration of 1&#xd7;10to 1&#xd7;10/cmand a thickness of 0.3 to 1.0 &#x3bc;m. The second silicon carbide semiconductor deposition layer has a surface defect density of 3 defects/cm.

Method of manufacturing a silicon carbide semiconductor device including depositing a second silicon carbide semiconductor on an etched silicon carbide base region

The SiC-IGBT includes a p-type collector layer, an n-type voltage-blocking-layer provided on the collector layer, p-type base regions provided on the n-type voltage-blocking-layer, n-type emitter regions provided in an upper portion of the p-type base region, a gate insulating film provided in an upper portion of the voltage-blocking-layer, and a gate electrode provided on the gate insulating film. The p-type buffer layer has thickness of five micrometers or more and 20 micrometers or less and is doped with Al at impurity concentration of 5&#xd7;10cmor more and 5&#xd7;10cmor less and doped with B at impurity concentration of 2&#xd7;10cmor more and less than 5&#xd7;10cm.

Silicon carbide epitaxial wafer, silicon carbide insulated gate bipolar transistor, and method of manufacturing the same

A silicon carbide semiconductor substrate, including a silicon carbide substrate of a first conductivity type, a buffer layer of the first conductivity type and an epitaxial layer of the first conductivity type. The silicon carbide substrate has a central part and a peripheral part surrounding the central part, and is doped with a first impurity that determines the first conductivity type. The buffer layer is provided on a front surface of the central part of the silicon carbide substrate, and is doped with the first impurity, of which a concentration is at least 1.0&#xd7;10/cm, and a second impurity different from the first impurity. The epitaxial layer is provided on a front surface of the peripheral part of the silicon carbide substrate, and is doped with the first impurity, of which a concentration is lower than the concentration of the first impurity in the buffer layer.

Silicon carbide semiconductor substrate, method of manufacturing silicon carbide semiconductor substrate, semiconductor device and method of manufacturing semiconductor device

In a vertical MOSFET having a trench gate structure, a lifetime killer region is provided in a p-type epitaxial layer formed by epitaxial growth. The lifetime killer region includes an electron lifetime killer that causes electrons entering the lifetime killer region to recombine and become extinct. As a result, the lifetime killer region decreases the electrons generated at the pn interface of the p-type epitaxial layer and an n-type drift layer and enables a configuration in which electrons are not delivered to the p-type epitaxial layer.

Silicon carbide semiconductor device and method of manufacturing a silicon carbide semiconductor device

A silicon carbide semiconductor device, including a silicon carbide substrate, a drift layer provided on a front surface of the silicon carbide substrate, an embedded layer selectively provided in a surface layer of the drift layer, an epitaxial layer provided on the drift layer, a channel layer provided on the epitaxial layer, a source region selectively provided in a surface layer of the channel layer, a trench penetrating the source region and the channel layer and reaching the epitaxial layer, a gate electrode provided in the trench via a gate insulating film, a source electrode in contact with the channel layer and the source region, and a drain electrode provided on a rear surface of the silicon carbide substrate. The embedded layer is arranged underneath the trench in a depth direction. A longitudinal direction of the trench, which is perpendicular to the depth direction, is parallel to the off-direction of the silicon carbide substrate.

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Tsukuba, Japan

Takeshi Tawara