Kabushiki Kaisha Toshiba

Takeshi Sunada

Yasukazu Mase

A method of manufacturing the semiconductor device comprises elements described below;

Semiconductor device, method for manufacturing the same, apparatus for

A method for manufacturing a semiconductor device comprises, after sequentially forming first and second insulating films over a semiconductor substrate, forming a lower interconnection layer formation groove by a lithography technique and anisotropic etching technique in the second insulating film and first insulating film. Then a lower interconnection layer material is formed over a whole surface of a resultant structure and it is removed, by a chemical/mechanical polishing technique, in a way to leave a portion as a buried interconnection layer in the lower interconnection layer formation groove. Then first and second insulating interlayers are subsequently formed over a whole surface of a resultant structure and an upper interconnection layer formation groove is formed in the second insulating interlayer. Then a via hole is formed in the first insulating interlayer at an area connecting an upper interconnection layer to a lower interconnection layer. The formation of the via hole is achieved by setting an etching rate of the first insulating interlayer to be over ten times that of the second insulating film and second insulating interlayer. After the formation of the via hole, an upper interconnection layer is formed as a buried layer in the upper interconnection formation groove and via hole and it is electrically connected to the lower interconnection layer.

Method for manufacturing a semiconductor device having interconnection

A conductive film is formed on first and second prospective lower wiring layer formation regions on a semiconductor substrate and a prospective isolation region between the lower wiring layers. An insulating interlayer is formed on the semiconductor substrate including this conductive film and is partially removed to obtain an opening in which the conductive film is exposed. In addition, an upper wiring layer is formed on the upper surface of the semiconductor substrate. The conductive film and an upper wiring portion located on the conductive film are simultaneously and selectively removed to obtain isolated upper layer portions and isolated conductive film portions. Alternatively, two wiring portions each having at least two lower wiring portions electrically insulated from each other and adjacent to each other are formed on a semiconductor substrate having a stepped portion, and an insulating interlayer is formed thereon. The insulating interlayer is removed until the first and second wiring portions are exposed. In addition, the stepped portion formed in the second wiring portion is buried with a third insulating film. A method of forming a highly reliable multilayered wiring structure at a high yield can be obtained.

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Ichikawa, Japan

Takeshi Sunada