Semiconductor Technology Academic Research Center

Takeshi Shoda

Kazuhiko Iwasaki

Satoshi Fukumoto

Masayuki Arai

Masayuki Sato

Junichi Nishimoto

Ken-ichi Ichino

An object of the invention is to drastically reduce the area overhead in a semiconductor integrated circuit incorporating a test configuration that uses a partially rotational scan circuit. To achieve this, in the semiconductor integrated circuit incorporating the test configuration that comprises a combinational circuit () and a scan chain () constructed by connecting a plurality of scan flip-flops () in a chain, the scan chain () is divided into a plurality of sub scan-chains (to) each of which has a partially rotational scan (PRS) function and a test response compaction (MISR) function. By performing a scan test in a plurality of steps while changing the combination of the sub scan-chains to be set as PRS and the sub scan-chains to be set as MISR, the test can be performed without having to provide a test response compactor separately from the scan chain, and thus the area overhead can be reduced.

Semiconductor integrated circuit incorporating test configuration and test method for the same

The purpose of the invention is to determine an optimum initial value to be input to a test pattern generator in order to achieve efficient testing of an integrated circuit. To achieve this purpose, a minimum test length is obtained by performing a fault simulation and a reverse-order fault simulation using an arbitrarily given initial value; the next initial value that is likely to yield a test length shorter than the minimum test length is computed and a fault simulation is performed using the thus computed initial value; and the next initial value that is likely to yield a test length shorter than that test length is computed and a fault simulation is performed using the thus computed initial value. By repeating this process, an initial value that yields the shortest test length is obtained.

Method and apparatus for determining optimum initial value for test pattern generator

Growing community of inventors

Kokubunji, Japan

Takeshi Shoda