Kabushiki Kaisha Toshiba

Kioxia Corporation

Toshiba Memory Corporation

Takeshi Shimane

Koji Hosono

Mitsuhiro Noguchi

Masaru Koyanagi

Hiroyuki Kutsukake

Dai Nakamura

Kenji Gomikawa

Takashi Aoi

Tadayoshi Uechi

Takashi Izumida

Norihisa Arai

Minori Kajimoto

Hiroyuki Kinoshita

Naoyuki Shigyo

Mutsuo Morikado

Atsuhiro Suzuki

Michihito Kono

Hiroshi Shimode

A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.

Non-volatile semiconductor storage device

A semiconductor device has a third region between first and second regions on a substrate surface. A gate insulating film which is above the third region. A gate electrode is above the gate insulating film and includes a metal-containing layer. A first conductor is above the gate electrode. A first voltage can be applied to the first conductor. A second conductor is above the first region. A second voltage can be applied to the second conductor. A third conductor is above the first region. A third voltage different from the first and second can be applied to the third conductor. A metal oxide film is provided between the first region and the third conductor. An upper surface of the metal oxide film includes a portion at a height from the substrate that is lower than a height of an upper surface of the metal-containing layer.

Semiconductor device and semiconductor storage device

A semiconductor memory device, includes: a first region including a memory cell array; and a second region including a peripheral circuit. The second region includes a semiconductor substrate having a first surface and a second surface. The semiconductor substrate includes: a semiconductor region between the first and second surfaces; an n-type semiconductor region provided on the first surface and higher in donor concentration than the semiconductor region; a damaged region provided on the second surface; and a p-type semiconductor region provided between the damaged region and the n-type semiconductor region, closer to the second surface than the n-type semiconductor region in a direction from the first surface toward the second surfaces of the semiconductor substrate, and higher in acceptor concentration than the semiconductor region.

Semiconductor memory device

A semiconductor device of an embodiment includes: a first and second semiconductor regions of a first conductivity type; a third semiconductor region of a second conductivity type disposed between the first and second semiconductor regions; a fourth semiconductor region of the first conductivity type disposed below the first semiconductor region; a fifth semiconductor region of the first conductivity type disposed below the second semiconductor region; a first region containing carbon disposed between the first and fourth semiconductor regions; a second region containing carbon disposed between the second and fifth semiconductor regions; a third region disposed between the first and second regions; the first and second regions having a first and second carbon concentrations respectively, the third region not containing carbon or having a lower carbon concentration than the first and second carbon concentrations in a portion below an end of a lower face of a gate electrode.

Semiconductor device

A semiconductor device according to an embodiment includes a semiconductor layer having a first plane and a second plane opposite to the first plane; a gate electrode; a gate insulating layer provided between the first plane and the gate electrode; and a pair of first p-type impurity regions provided in the semiconductor layer on both sides of the gate electrode, containing boron, carbon, and germanium, having a bond structure of boron and carbon, having a first boron concentration and a first depth in a direction from the first plane toward the second plane, and having a distance between the first p-type impurity regions being a first distance.

Semiconductor device and semiconductor memory device

According to an aspect of the present invention, there is provided a semiconductor device including: a semiconductor substrate; active areas with island-like shapes formed on the semiconductor substrate; an element isolation area surrounding the active areas and including an element isolation groove formed on the semiconductor substrate and an element isolation film embedded into the element isolation groove; gate insulating films each formed on corresponding one of the active areas and having a first end portion that overhangs from the corresponding active area onto the element isolation area at one side and a second end portion that overhangs from the corresponding active area onto the element isolation area at the other side, wherein an overhang of the first end portion has a different length from a length of an overhang of the second end portion.

Semiconductor device and manufacturing method thereof

According to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cells without a source region and a drain region, and a first insulating film. The memory cells are arranged adjacent to one another on the semiconductor substrate and include a first gate electrode including a charge accumulation layer. A current path functioning as a source region or a drain region of a selected memory cell is formed in the semiconductor substrate when a voltage is applied to the first gate electrode of one of unselected memory cells. The first insulating film is formed on the semiconductor substrate to fill a region between the first gate electrodes of the memory cells adjacent to each other.

Semiconductor memory device including charge accumulation layer

A semiconductor device has source and drain regions, a gate insulating film, a gate electrode, and a channel region. The channel region includes a region where carriers move between the source and drain regions. An impurity concentration of the channel region is higher at an end portion of a surface depletion layer than at an interface between the semiconductor layer and the gate insulating film. The impurity concentration varies along a direction in which the gate electrode, the gate insulating film and the channel region are successively provided, and it increases substantially linearly near the end portion of the surface depletion layer.

Growing community of inventors

Matsudo, Japan

Takeshi Shimane