Fujitsu Corporation

Takeshi Shimada

Shinya Hatakeyama

Tatsuru Nakagaki

Akihiro Kobayashi

Kiyohisa Hoshino

Junichi Ehara

Ken Takashima

Soichi Kato

A mobile communication system has a mobile terminal, basestations, and a Radio Network Controller (RNC). In the case where drop of a frame occurs during data communication in Iub/Iur (between the basestations and the RNC), the RNC executes retransmission of an EDCH FP frame between the RNC and the basestations by transmitting a TN frame to the basestations to repair the drop of the frame without executing retransmission with the terminal device.

Control apparatus, wireless communication apparatus, communication system, and control method

A mobile communication system in which a mobile station copies data and transmits that copied data to a plurality of base stations, each base station sends that copied data to a serving radio network control device (S-RNC) directly or via a drift radio network control device (D-RNC), and the S-RNC selectively combines and outputs the received copied data; wherein a congestion monitoring unit monitors the congestion state of a line between the D-RNC and S-RNC, and when that line is congested, a D-RNC selectively combines the copied data that is inputted from the plurality of base stations and sends the result to that line, and when the line is not congested, the D-RNC sends the copied data that is inputted from the plurality of base stations to the line without performing selective combination.

Communication method and radio network control device in a mobile communication system

Data transmission for writing data into a shared memory is performed by a high-speed dedicated line provided between each processor and the shared memory. When a processor performs writing to a shared memory space, the processor notifies an update notification bus corresponding to the conventional global bus, to which address the update is to be performed. The other processors which have detected this notification inhibit access to that address and wait for the write data to be sent to the address via the dedicated line. When the data has arrived, the data is written into the corresponding address. Here, the data is also written into the corresponding address, thereby maintaining the cache coherency. Moreover, when transmitting a write address, it is necessary to acquire the bus use right while data transmission is performed by using the dedicated line, which significantly reduces the time required for acquiring the bus use right.

Multi-processor system

Growing community of inventors

Kawasaki, Japan

Takeshi Shimada