Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Takeshi Shima

Tetsuro Itakura

Yukio Kamatani

Ken-Ichi Torii

Takashi Taguchi

Tomohisa Kimura

An amplifier circuit including an input stage and an output stage which are cascade-connected between a signal input terminal to which an input signal is input and a signal output terminal to which a capacitive load is connected, and which includes at least an input amplification stage and an output amplification stage, and a resistor circuit including at least a resistor inserted between the output terminal of the output amplification stage and the signal output terminal.

Amplifier circuit and liquid-crystal display unit using the same

A D/A conversion circuit which can perform D/A conversion at high speed and with high precision is disclosed. The D/A conversion circuit comprises an analog reference power supply, an output buffer, a multiplexer, a pre-buffer, and a current changeover switch. The pre-buffer operates with a power supply voltage different from that of the analog reference power supply, and outputs a voltage substantially equal to an output voltage of the analog reference power supply. For a predetermined period after logic of digital data changes, the output voltage of the pre-buffer is supplied to the output buffer, and an input parasitic capacitor of the output buffer is charged/discharged. After the predetermined period elapses, the output voltage of the analog reference power supply is supplied to the output buffer. Therefore, a charging/discharging current of the input parasitic capacitor does not flow through the analog reference power supply, and fluctuation of the output voltage of the analog reference power supply can be suppressed.

D/A conversion circuit and liquid crystal display device

An amplifier circuit comprising an input stage and an output stage which are cascade-connected between a signal input terminal to which an input signal is input and a signal output terminal to which a capacitive load is connected and which includes at least an input amplification stage and an output amplification stage, and a resistor circuit including at least a resistor inserted between the output terminal of the output amplification stage and the signal output terminal.

An analog-to-digital converter circuit, such as a flash-type A/D converter, has a plurality of voltage comparators. Each voltage comparator has first and second input terminals and an output terminal. The voltage comparators are arranged in order of reference voltages V.sub.ref1, V.sub.ref2, V.sub.ref3, V.sub.ref4, and V.sub.ref5 supplied to the respective second input terminals of the voltage comparators. Each voltage comparator is connected to the adjacent voltage comparator and the adjacent voltage comparator but one via a first resistor and a second resistor, respectively. The presence of the second resistors makes it possible to improve the degree of contributions of the voltage comparators positioned farther away from the center comparator. Accordingly, conversion deviations are reduced when the outputs of the respective comparators are added and averaged, thereby enhancing conversion precision. As a consequence, the voltage comparators are improved in comparison precision and comparison speed.

Analog-to-digital converter circuit

A signal processing apparatus includes a switching unit for switching one input signal to be processed and outputting the switched signal. Signal processing units have the same structure, and each of the signal processing units comprises a plurality of signal processors for subjecting an input signal to be processed to predetermined signal processing. Each signal processor has an inherent signal processing error. A control unit controls a switching operation of the switching unit so that the switched signal output from the switching unit is input to an arbitrary combination of the signal processors. A synthesizing unit synthesizes outputs from the arbitrary combination of signal processors and produces one output signal in which the inherent signal processing error of each signal processor has been averaged.

Signal processing apparatus capable of reducing conversion error of a

A neural network apparatus includes a neural network including at least two neuron layers each having a plurality of neurons and at least one synapse layer having a plurality of synapses each arranged between the neuron layers, each synapse storing a weight value between the neurons and multiplying the weight value with an output value from each of the neurons in the previous-stage neuron layer to output a product to the next-stage neuron layer, a section for causing an error signal between an output from the neural network and a desired output to back-propagate from an output-side neuron layer to an input-side neuron layer of the neural network, a learning control section for updating the weight value in the synapse on the basis of the error signal and the output value from the previous-stage neuron, and a selecting section for selecting a synapse whose weight value is to be updated by the learning control section when the learning control section is to update the weight values of a predetermined number of synapses in a predetermined order.

Neural network apparatus and learning method thereof

A capacitative load driving circuit is provided in a liquid crystal display device and has an input selection circuit having a wide and effective voltage range of an input signal. The driving circuit changes over through source or emitter followers formed by two types of conductivity, for detecting as to whether or not a potential of the input signal is in an input voltage range of a differential amplifier circuit constituting a voltage follower after selecting at least one input signal through any of source or emitter followers.

Capacitive load driving circuit including input selection circuit and

A sample-and-hold circuit device capable of realizing a high-precision and high-speed operation, in which the output signal is independent of the error signal caused by a MOS transistor. The circuit includes a first switch coupled between an input terminal and a first internal terminal, a second switch coupled between the first internal terminal and a second internal terminal, a capacitor coupled between the second internal terminal and a reference potential, a buffer for transferring a potential held in the capacitor to an output terminal, a control signal generator for controlling the first switch to turn off after the second switch is turned off, and then to again turn on the second switch so as to replace an error charge into the second switch.

Sample-and-hold circuit device

A neural network with a learning function which does not require the backward propagation of the signals for the learning, which is applicable for a case involving the feedback of the synapses or the loop formed by the synapses, and which enables the construction of a large scale neural network by using compact and inexpensive circuit elements. An evaluation value is calculated according to a difference between each output signal of the network and a corresponding teacher signal; a manner of updating the synapse weight factor of each synapse is determined according to an evaluation value change between a present value and a previous value of evaluation value on a basis of the simulated annealing; a randomly changing update control signal is generated according to a random number; and a synapse weight factor of each synapse is updated according to the generated update control signal and the determined manner of updating on a basis of the Monte-Carlo method.

Neural network with learning function based on simulated annealing and

A sample-and-hold circuit device which includes a plurality of sample-and-hold circuits and a comparator/amplifier for comparing a reference potential with an output signal which is output from the plurality of sample-and-hold circuits so as to amplify a difference between these two signals. An output of the comparator/amplifier is fed back to respective control terminals of the different sample-and-hold circuits, each being provided as a level control signal. In another embodiment, a plurality of adding circuits are provided for adding the outputs of the plurality of sample-and-hold circuits and then comparing this value with an arbitrary reference potential, whereby a difference between the sum value and the arbitrary reference potential is amplified and fed back to the control terminals of the sample-and-hold circuits.

A sample-and-hold circuit includes a first switch element which is opened or closed in accordance with a first control signal so as to selectively connect an input signal terminal for receiving an input signal to an internal terminal, a non-linear element for connecting the internal terminal to an output terminal, a potential holding circuit connected between the output terminal and ground, and a second switch element or a current source circuit which is controlled by a second control signal so as to selectively connect the output terminal to ground.

This invention has an object to provide a practical neural network device. The first neural network device of this invention comprises an input circuit for performing predetermined processing of external input information and generating an input signal, an arithmetic processing circuit for performing an arithmetic operation of the input signal in accordance with a plurality of control parameters and generating an output signal, and a control circuit for controlling the control parameters of the arithmetic processing circuit so that the output signal is set to satisfy a predetermined relationship with the input signal, the control circuit including a first cumulative adder for performing cumulative summation of updating amounts of the control parameters for a plurality of proposition patterns supplied as the input signal during learning, and a second cumulative adder for adding currently used control parameter values to values obtained by the first cumulative adder to obtain new control parameter values.

Neural network device

An analog storage device employs an electrically erasable programmable transistor as its memory cell. The memory cell transistor has a source and a drain which are disposed spaced apart from each other on a semiconductive substrate to define a channel region therebetween, an insulated floating gate electrode which at least overlaps the channel region, and an insulated control gate electrode disposed above the insulated floating gate electrode. Minority carriers are allowed to tunnel between the channel region and the insulated floating gate. The amount of carriers to be stored on the floating gate electrode is controlled such that it is in proportion to analog data to be stored therein. A variation in the internal field of the transistor which may occur when its floating gate electrode is being charged with minority carriers is monitored. When a field variation is detected, a voltage for compensating for the detected field variation is applied to the control gate electrode, whereby the linearity of analog storage is ensured.

Analog storage device for artificial neural network system

A multi-layer perceptron circuit device using integrated configuration which is capable of incorporating self-learning function and which is easily extendable. The device includes: at least one synapse blocks containing: a plurality of synapses for performing weight calculation on input signals to obtain output signals, which are arranged in planar array defined by a first and a second directions; input signal lines for transmitting the input signals to the synapses, arranged along the first direction; and output signal lines for transmitting the output signal from the synapses, arranged along the second direction not identical to the first direction; at least one input neuron blocks containing a plurality of neurons to be connected with the input signal lines; and at least one output neuron blocks containing a plurality of neurons to be connected with the output signal lines.

Growing community of inventors

Sagamihara, Japan

Takeshi Shima