Hitachi, Ltd.

Takeshi Shigeno

Tetsuhiro Goto

Yoshihiro Toyohara

Megumu Hasegawa

Yuzuru Maya

Akira Otsuji

Takashi Morikawa

In a data processing system which runs a plurality of operating systems, a channel device can be shared by the plurality of operating systems. In addition, a channel device which supports port multiplexing can also be shared by a plurality of operating systems. The channel device includes a plurality of IDs each indicating that the channel device is a medium for performing input/output processing, and an input/output processing controller for assigning one operating system to each of the IDs, and controlling a data transfer independently for each ID to control a plurality of data transfers. Further, in a channel device which has a plurality of ports, an input/output processing controller is provided for assigning an operating system to each of the ports, and transferring data independently for each port to control the plurality of ports.

Data processing system running on a plurality of operating systems (OS) and enabling a channel device to simultaneously perform processing associated with the plurality of operating systems

Data processing system

A data processing apparatus has a basic processing unit (BPU),a channel processor (CHP),message channel units (MCH),n, message channel receivers (MCHR),m connected respectively to the message channel units,n, and a structured external storage device (SES),which may be connected to a plurality of hosts via the message channel receivers,m and which includes a cache memory,for accommodating data shared by the hosts. Before issuing a synchronous instruction, a program issues an instruction notifying in advance the inventive apparatus of the intended use of hardware resources. When the hardware resources are reserved by the notifying instruction, the apparatus guarantees the subsequent execution of the synchronous instruction. Because synchronous instructions are always carried out, the system overhead is lowered.

Data processing apparatus for executing synchronous instructions prior to executing asynchronous instructions

A data transfer method for a computer system in which a computer is logically divided into a plurality of logical processing units and a logical coupling unit. A correspondence between a start of physical addresses of a memory of each logical processing units in a memory of the computer is stored in advance. If a first logical processing unit issues a write command to the logical coupling unit by designating a logical address of data, the logical coupling unit stores an identifier and the logical address of the first logical processing unit. If a second logical processing unit issues a read command of the data, a physical address of data storage corresponding to the logical address of the first logical processing unit is calculated in accordance with the identifier and the logical address of the first logical processing unit and the address correspondence. The data is read by using the calculated physical address.

Data transfer method for logical computers

Growing community of inventors

Hadano, Japan

Takeshi Shigeno