Renesas Technology Corp.

Takeshi Shibagaki

Hiromi Fujita

Masanori Kurimoto

Shigeru Kuriyama

Chie Hiramine

Masahiko Oomura

The outputting of an output pulse produced in response to the inputting of a data pulse and a clock pulse to a D type flip-flop circuit is repeatedly simulated in a simulation process to extract a pulse time difference between the data pulse and the clock pulse as a timing verification checking value in a checking value extracting process on condition that the level of the output pulse becomes higher than a reference voltage until a simulation completion time and the pulse time difference is within a prescribed range. After the first simulation, an optimum simulation completion time, at which the levels of the data pulse, the clock pulse and the output pulse are respectively set to a constant high value, is determined to be place the optimum simulation completion time between a simulation start time and the simulation completion time, and the level of the output pulse is checked at the optimum simulation completion time in simulations following the first simulation. Therefore, a pulse time difference sufficiently made small can be rapidly and reliably extracted as a timing verification checking value.

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Tokyo, Japan

Takeshi Shibagaki