Fujitsu Corporation

Yokohama City University

Toyo Garasu Kabushiki Kaisha

Takeshi Sasaki

Hideo Monma

Shinji Sato

Koichi Yamashita

Yoshio Hirose

Akihiro Yasuo

Jinichi Yoshizawa

Yoshihiro Yamato

Tatsuya Oku

Ichiro Aoki

Eiji Maeda

Tsuguo Okada

Akihide Ryo

Shigeki Kawahara

Masayuki Takasaka

Masatoshi Kishida

Yoshinori Enomoto

Shunzo Ohta

Ataru Kumagai

Yoshinori Okuda

Masao Maeda

Akira Yamamori

A method for determining probability that prostate cancer will metastasize, as well as a diagnostic reagent used therefor is disclosed. It was discovered that the percentage that NF-&#x3ba;B-p65/RelA has the 254th amino acid threonine which is phosphorylated is significantly higher in the prostate cancer cells in the cases where the bone metastasis was observed than in the cases where bone metastasis was not observed. Thus, the method for determining probability that prostate cancer will metastasize comprises measuring human NF-&#x3ba;B-p65/RelA in which 254th amino acid threonine is phosphorylated, which human NF-&#x3ba;B-p65/RelA is contained in a prostate tissue separated from human.

Method for determination of prognosis of prostate cancer, and diagnostic agent for use in the method

In multi-connections, a message writing apparatus is provided. This message writing apparatus () comprises a path recognizing section (), a received message assembling section (), a receive control section (), an arbitrating section () and an external memory control section (). When a received ATM cell is written/readout in/from a receiving buffer, it is written/read out in a memory area corresponding to each path, which enables the processing of AAL5 messages from a plurality of paths and improves the transfer processing capability, thereby leading to realizing a shortening of the data transfer time.

Message writing apparatus, message writing method, message readout apparatus, message readout method, memory address control circuit for writing of variable-length message and memory address control circuit for readout of variable-length message

A semiconductor integrated circuit device provides; a master chip including a basic cell region having a plurality of basic cell arrays arranged thereon, for forming various kinds of circuits. An input/output cell region provides a plurality of input/output cells arranged along the periphery of the basic cell region. A first wiring layer is formed on the basic cell region and the input/output cell region via a first insulation layer and has contact holes at predetermined positions. The first wiring layer includes fixed wirings irrespective of the kind of circuit to be formed. A second wiring layer is formed on the first wiring layer via a second insulation layer having through holes at predetermined positions. The second wiring layer includes programmed wirings to specify the kind of circuit to be formed. Only the wiring pattern of the second wiring layer is suitably changed in accordance with the kind of circuits to be formed and connected among the input/output cell region, basic cell regions in regions corresponding to the input/output cell regions and the basic cell region, thereby greatly reducing a turnaround time of the device.

Method of producing a semiconductor integrated circuit device using a

A semiconductor device comprises a test signal generating circuit for generating a test signal having an arbitrary frequency, a first buffer for selectively outputting one of the test signal and an external input signal, at least one test circuit supplied with an output signal of the first buffer, an external output terminal, a logic circuit, a second buffer for selectively supplying to the external terminal one of the test signal from the test circuit and an output signal of the logic circuit, and a switching signal generating circuit for generating switching signals for the first and second buffers. The state of the test circuit is checked by use of the test signal to indirectly determine the state of the logic circuit.

Semiconductor device having a test circuit

In the fabrication of a plastic sleeve by heat sealing overlapped ends of a plastic film blank wrapped around a mandrel, a part of the underlying overlapped end is often melted inadvertently and adheres to the mandrel, obstructing easy stripping of the sleeve off the mandrel. Accordingly, a tensioning groove is formed in the mandrel surface, and a pressing-in bar is pressed thereinto over the sleeve while a part of the sleeve is held stationary against the mandrel by a holding plate to pull the sleeve part thus adhering sidewise in the peripheral direction of the mandrel and thereby to peel away and free the same.

Method and device for the fabrication of plastic sleeves

A circuit for checking the integrity of interconnections between chips in a chip-on-chip type IC device is fabricated in respective portions on the lower and upper chips in peripheral areas thereof intermediate the inner logic circuit of each chip and the corresponding bonding pads. Selection circuits connected between the inner logic circuit signal terminals and the corresponding bonding pads of the chip are switched by control signals to be isolated and permit normal operation of the chip or to a checking mode to isolate the inner logic circuit and permit transmission of test signals through the interconnections. The test signals received through the interconnections are compared with the test signals as transmitted to determine the integrity of the individual interconnections. The disclosed apparatus and method provide for testing of the integrity of interconnections defining single direction signal paths of individual interconnections, as between the upper and lower chips, and for selectively bidirectional transmission through the individual interconnections.

Chip on chip type integrated circuit device

Growing community of inventors

Yokohama, Japan

Takeshi Sasaki