Hitachi, Ltd.

Renesas Technology Corp.

Elpida Memory, Inc.

Other

Hitachi Ulsi Systems Co., Ltd.

Renesas Electronics Corporation

Hitachi Device Engineering Co., Ltd.

Mitsubishi Electric Corporation

Hitachi Ulsi Engineering Corp.

Takeshi Sakata

Kiyoo Itoh

Masashi Horiguchi

Satoru Hanzawa

Tomonori Sekiguchi

Masakazu Aoki

Riichiro Takemura

Hideyuki Matsuoka

Kazuhiko Kajigaya

Takayuki Kawahara

Katsutaka Kimura

Osamu Nagashima

Kunio Uchiyama

Hiroyuki Mizuno

Takao Watanabe

Yusuke Kanno

Hiromasa Noda

Tomoyuki Ishii

Toshiaki Yamanaka

Yoshinobu Nakagome

Kan Takeuchi

Kazuo Yano

Takashi Hashimoto

Koichi Seki

Youji Idei

Nobuhiro Oodaira

Motoyasu Terao

Shinichi Miyatake

Sadayuki Morita

Shinichiro Kimura

Kazushige Ayukawa

Taro Osabe

Takahiro Sonoda

Haruko Tadokoro

Hiroki Fujisawa

Ryoichi Hori

Katsuro Watanabe

Kenchi Ito

Yuichi Okuda

Norikatsu Takaura

Ryoichi Kurihara

Takashi Sato

Kenichi Osada

Toshihiko Tanaka

Hitoshi Tanaka

Hideaki Kurata

Masanori Isoda

Shin'ichiro Kimura

Bryan Atwood

Katsumi Matsuno

Hiroshi Ichikawa

Koichiro Ishibashi

Kazumasa Yanagisawa

Masayuki Miyazaki

Kazuyuki Miyazawa

Jun Etoh

Masaru Kokubo

Hirokazu Aoki

Kiyoshi Hasegawa

Masafumi Ohi

Nobuyasu Kanekawa

Goro Kitsukawa

Satoru Akiyama

Tsugio Takahashi

Yoshiki Kawajiri

Takesada Akiba

Takaaki Iwata

Tatsushi Sato

Shigeru Matsuno

Makoto Saen

Yoshihito Imai

Yoichiro Nishimoto

Junji Shigeta

Tomoko Sendai

Takeyuki Maegawa

Teiji Takahashi

Tsuyoshi Kachi

Shin&prime;ichiro Kimura

Shin' Ichiro Kimura

Masashi Ohkawa

Provided is a semiconductor device capable of reducing a penalty associated with ensuring reliability. The semiconductor device includes a latch circuit which has input/output paths of three systems or more independent from each other. The latch circuit includes a plurality of storage elements STEto STEwhich are provided on the input/output paths of the three systems or more, respectively, and hold input data in synchronization with a clock signal. At least one storage element (for example, STE) of the plurality of storage elements STEto STEincludes a majority decision unit (for example,) executing a majority decision using data from the storage elements provided on other input/output paths different from the input/output path thereof and outputs data in which a result of the majority decision is reflected.

Semiconductor device

In a device including a programmable circuit, the programmable circuit is connected to a non-volatile memory in which configuration information is stored, and another memory having a faster reading speed than the non-volatile memory, and the programmable circuit includes a configuration memory control circuit, and a signal line group for performing reading with respect to the other memory such as a volatile memory and an embedded memory from the non-volatile memory by the configuration memory control circuit, and copies a part of circuit configuration information which is required to be subjected to fast restoration from failure into the other memory.

Programmable circuit device and configuration information restoration method

In a sense circuit for DRAM memory cell a switch is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.

The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.

Provided are a wire electric discharge machining method for poorly conductive materials, such as solar cell silicon, and a semiconductor wafer manufacturing method and a solar battery cell manufacturing method based on the wire electric discharge machining method. Electrical discharge machining of a high volume resistivity, hard and brittle materials, having a volume resistivity that is equal to or higher than 0.5 &#x3a9;&#xb7;cm and equal to or lower than 5 &#x3a9;&#xb7;cm is performed by applying a pulse voltage having a pulse width that is equal to or higher than 1 &#x3bc;sec and equal to or lower than 4 &#x3bc;sec and having a peak current at the time of machining a wire electrode that is equal to or higher than 10A and equal to or lower than 50A to a wire electrode and generating a discharge pulse between the wire electrode and a subject to be machined.

Wire electric discharge machining method, semiconductor wafer manufacturing method, and solar battery cell manufacturing method

A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed.

Semiconductor integrated circuits with power reduction mechanism

A dummy cell includes a plurality of first memory cells MC for storing '1' or '0', arranged at points of intersection between a plurality of word lines WRto WRand a plurality of first data lines Dto D, a plurality of first dummy cells MCH for storing &#x201c;1&#x201d; or &#x201c;0&#x201d;, arranged at points of intersection between the word lines WRto WRand a first dummy data line, and a plurality of second dummy cells MCL for storing &#x201c;0&#x201d;, arranged at points of intersection between the word lines WRto WRand a second dummy data line DD

A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.

Sense amplifier for semiconductor memory device

The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such that any bit must be the logical value '1'; Match-lines are hierarchically structured and memory cells are arranged at the intersecting points of a plurality of sub-match lines and a plurality of search lines; Further the sub-match lines are connected to main-match lines through the sub-match detectors, respectively and main-match detectors are arranged on the main-match lines.

Content addressable memory device

The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to bit line LBL.

A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

Semiconductor integrated circuit device having power reduction mechanism

The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected wordline conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.

Storage device

A semiconductor device employs a SESO memory or a phase change memory which has a smaller memory cell area than SRAM. The semiconductor device has a plurality of memory banks each composed of the SESO or phase change memories, and a cache memory which has a number of ways equal to the ratio of a write speed (m) to a read speed (n). The semiconductor device controls the cache memory such that a write back operation is not repeated on the same memory bank.

Growing community of inventors

Hino, Japan

Takeshi Sakata