Other

Hitachi, Ltd.

Renesas Technology Corp.

Renesas Electronics Corporation

Hitachi Ulsi Systems Co., Ltd.

Hitachi Ulsi Systems C O., Ltd.

Takeshi Saikawa

Norio Suzuki

Katsuhiko Hotta

Hidenori Sato

Akira Takamatsu

Hiroyuki Maruyama

Hiroyuki Ichizoe

Tsuyoshi Fujiwara

Tsuyoshi Tamaru

Sadayuki Okudaira

Toshinori Imai

Yoshiyuki Okabe

Ryouichi Furukawa

Masato Kunitomo

Kazutoshi Ohmori

Tetsuo Saito

Mitsuhiro Toya

Shunji Mori

Ryohei Maeno

Yoshinori Kawasaki

Provided is a technology capable of reducing parasitic capacitance of a capacitor while reducing the space occupied by the capacitor. A stacked structure is obtained by forming, over a capacitor composed of a lower electrode, a capacitor insulating film and an intermediate electrode, another capacitor composed of the intermediate electrode, another capacitor insulating film and an upper electrode. Since the intermediate electrode has a step difference, each of the distance between the intermediate electrode and lower electrode and the distance between the intermediate electrode and upper electrode in a region other than the capacitor formation region becomes greater than that in the capacitor formation region. For example, the lower electrode is brought into direct contact with the capacitor insulating film in the capacitor formation region, while the lower electrode is not brought into direct contact with the capacitor insulating film in the region other than the capacitor formation region.

Semiconductor device, RF-IC and manufacturing method of the same

A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film. The method may also include the step of forming dummy patters in a relatively large isolation region of isolation regions with relatively different planar dimensions before the first insulating film is deposited.

Method of manufacturing a semiconductor integrated circuit device that includes forming an isolation trench around active regions and filling the trench with two insulating films

Method of manufacturing a semiconductor integrated circuit device that includes forming dummy patterns in an isolation region prior to filling with insulating material

A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film. The method may also include the step of forming dummy patterns in a relatively large isolation region of isolation regions with relatively different planar dimensions before the first insulating film is deposited

Method for manufacturing a semiconductor integrated circuit device that includes covering the bottom of an isolation trench with spin-on glass and etching back the spin-on glass to a predetermined depth

Manufacturing method of semiconductor device

A silicon oxide film on which a capacitor of a semiconductor integrated circuit device is formed is formed by the plasma CVD method at a temperature of 450&deg; C. to 700&deg; C. In this semiconductor integrated circuit device, a memory cell formed of a MISFET for data transfer and a capacitor is formed in a memory cell forming area, and an n channel MISFET and a p channel MISFET constituting a logic circuit is formed in a logic circuit forming area. As a result, the amount of degassing from the silicon oxide film can be reduced. Therefore, the growth of silicon grains on a surface of the silicon film constituting a lower electrode of the capacitor is not hindered by the degassing, and it becomes possible to increase the capacitance. Also, the step of a heat treatment for removing the moisture and the like after forming the silicon oxide film can be omitted, and it becomes possible to prevent the deterioration of the property of the MISFET.

Method of manufacturing semiconductor integrated circuit device comprising a memory cell and a capacitor

In order to fill in an isolation trench formed on a semiconductor substrate, the isolation trench is filled up to a predetermined middle position with a coating film first, and then an insulating film formed by a CVD method is deposited thereon. Additionally, the insulating film is polished by a CMP method, for example, so as to be ground. Thus, the isolation trench is filled with stacked films of the coating film and the insulating film. Further, an electrode pattern and a dummy pattern are formed on the semiconductor substrate, and the trench formed between these patterns is filled up to a predetermined middle position in its depth direction with the coating film. Then, a remaining depth portion of the trench is filled with the insulating film formed by a CVD method.

Method of manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device

Growing community of inventors

Ome, Japan

Takeshi Saikawa