Sony Corporation

Nissan Motor Company Limited

Hitachi, Ltd.

Takeshi Onodera

Yoshihiro Takiyasu

Mitsuo Asai

Koichi Morita

Tomoyuki Ishida

Hirofumi Yamashita

Ichiro Kumata

Makoto Iwasa

Norihisa Tsujimura

Tatsunori Tanigaki

Toshifumi Takamatsu

Miho Iwanaga

Nobuyoshi Suzuki

Yasutsune Terashima

Tomokazu Maeda

Takenori Sugawara

Ryuichi Ohno

Nozomu Hirose

A vehicle installed battery pack is provided with a pressure release structure. The vehicle installed battery pack includes a battery pack case, a battery pack module. The battery pack case includes a battery pack lower frame and a battery pack upper cover. The battery pack module is disposed in the battery pack lower frame. The battery pack upper cover is securely joined to the battery pack lower frame via a seal member that extends continuously about an entire perimeter of respective outside peripheral edge portion of the battery pack upper cover. The battery pack upper cover includes a deforming stepped portion having a height difference at least in a heightwise direction; and a weakly joined portion having a lower joint strength than other joined portions being set in an area of the seal member extending continuously about the entire perimeter. The area corresponds to the deforming stepped portion.

Vehicle installed battery pack with pressure release structure

An object of the present invention is to secure both of vehicle body floor upper space and battery mounting space, in setting of a mounting position of a high-power cut-off switch to a battery pack case. Battery pack casehaving battery modulesand SD switchthat cuts off battery high-power circuit by manual operation is arranged in a lower position of vehicle body floor. In this battery pack structure for electric vehicle, an inside space of the battery pack caseis divided into two areas in a vehicle front-and-rear direction, and one of the two areas is defined as a battery module mounting area. SD switchis provided in an upper surface position of the case that covers an electrical component mounting area, which is the other area, located on a vehicle front side with respect to battery module mounting area

Battery pack structure for electric vehicles

A structure for a vehicle body lower portion according to the present invention includes: a side sill () located on each side in a vehicle width direction and extending in a vehicle front-rear direction; a side member () joined to a lower face () of a floor panel () and extending in the vehicle front-rear direction at a position above the side sill () and inside the side sill () in the vehicle width direction; a brace member () connecting a lower part of the side member () to an upper side of the side sill (); and an outer cross member () connecting the lower part of the side member () to a lower side of the side sill ().

Structure for vehicle body lower portion

A vehicle underfloor structure includes under covers () that cover an underside of a vehicle, and drain members (D) provided in the under covers (). The drain members (D) each include: a front inclined wall () provided with a water drain opening (); and a rear inclined wall (). A recess is formed in each under cover in a front-back direction of the vehicle in such a manner that a first interior angle (&#x3b8;) formed by the front inclined wall is larger than a second interior angle (&#x3b8;) formed by the rear inclined wall and a length of the front inclined wall is different from a length of the rear inclined wall.

Vehicle underfloor structure

A test device that makes a test of a circuit device including a plurality of modules being substitutable in terms of function for one another, and in which a function change can be made for assignment to each of the modules based on an incoming control signal. The test device includes: a control section that generates the control signal, without changing a function to be assigned to a whole of the modules, to make the function change for assignment to each of the modules at least in a group of the modules; and a determination section that detects whether the circuit device operates differently when the function change is made for assignment to the modules, and based on a detection result, determines whether or not at least the group of the modules includes a defective module.

Test device and method for circuit device and manufacturing method for the same

Disclosed herein is a circuit apparatus including: plural modules having functions which can be substituted for each other; a function allocation section configured to set a one-on-one corresponding relationship between a plurality of predetermined functions and the plural modules in response to a control signal inputted thereto and allocate the functions coordinated in accordance with the one-on-one relationship individually to the modules; and first power inputting sections configured to input power supplies to be supplied to the modules. The apparatus further includes: second power inputting sections configured to input power supplies each corresponding to at least one of the functions; and a connection section configured to connect at least some of the first power inputting sections and the second power inputting sections so that each of the power supplies inputted by the second power inputting sections is supplied to that one of the modules to which a function corresponding to the power supply is allocated.

Circuit apparatus and fabrication method for circuit apparatus

A scan path circuit having a plurality of scan chain circuits includes a data compression circuit for data-compressing the outputs of the scan chain circuits and delivering the compressed outputs, and a selection circuit for switching the inputs of the scan chain circuits. The selection circuit switches an operation mode selectively in accordance with a predetermined control signal in such a manner that, in a first operation mode, an input signal obtained from a predetermined input terminal is delivered to the first and second scan chain circuits, and in a second operation mode, the input signal is delivered to the first and third scan chain circuits. Accordingly, the logic circuit can be tested with certainty in a short required time by the simplified structure.

Scan path circuit having a selection circuit for delivering an input signal to selected scan chain circuits

A semiconductor memory device is provided which includes: a plurality of memory cells each formed by latch means; gated clock circuits for writing identical data to all of the memory cells in response to a simultaneous writing signal supplied thereto; inverters for inverting data outputted from the memory cells; and selectors for selectively writing the inverted data to the memory cells.

Semiconductor memory device and method of testing same

A video displaying method of displaying, on a display unit, contents of video files. Each of the video files is composed of a plurality of images. The video displaying method includes the steps of extracting, from one of the video files, a plurality of images at predetermined intervals from the images composing the video file; displaying the extracted images on the display unit; in response to a selection of one image from the displayed images, reproducing the video file including the selected image beginning at a position of the selected image in the video file; and displaying the reproduced video file on the display unit.

Video searching method, apparatus, and program product, producing a group image file from images extracted at predetermined intervals

A video searching method, and apparatus, having a function of representing a video file are provided such that the contents of video files stored in a storage device may be recognized definitely and rapidly. The video searching apparatus includes a computer, a storage device, a device for controlling them, and a display device. The apparatus includes a software resource for producing a group image formed of at least two still images of scenes representing the contents of each of video files stored in the storage device. In the apparatus, the size of the group image is changed at any time. In response to manipulation of the group image, file operation such as deletion, movement or name change of a corresponding video file is performed.

Video searching method and apparatus, video information producing method, and storage medium for storing processing program thereof

A semiconductor circuit for compressing or encoding output data of a scan path circuit, able to realize a circuit test and fault analysis by the scan path circuit, and capable of preventing the configuration of a combinational circuit from being guessed from the input and output. Predetermined mode key data is input by being mixed in input data to a scan path circuit during a scan mode operation so as to be fetched by a mode key circuit embedded in the scan path circuit. The mode key data is fetched by the mode holding circuit from the mode key circuit and a mode signal BE is generated in accordance with the mode key data during a system mode operation. When the mode key data has a predetermined pattern, the mode key signal becomes a predetermined set value, and an output signal of the scan path circuit is output as it is in accordance therewith. Otherwise, since the output signal of the scan path circuit is encoded and output, the output of the scan path circuit can be concealed in accordance with need.

Semiconductor circuit having scan path circuit

When an access request is generated from a client in a network file server comprising a computer including a communication controller connected to at least one client through a network and transferring information on a plurality of addresses inside a main storage device as one packet to at least one client, the main storage device having a buffer, a central processing unit and an input/output bus for mutually connecting the communication controller, the central processing unit and the main storage device, and a secondary storage device connected to the computer, an area for storing the data corresponding to this access request is allocated into the buffer of the main storage device. The data corresponding to the access request is read out from the secondary storage device, is transferred to the buffer and is stored in the allocated area. A header for the data in the allocated area in the buffer, the address and size of the header and the address and size of the data are generated in the main storage device on the basis of the access request. As the address and size of the header and the address and size of the data are reported to the communication controller, the data inside the allocated area in the buffer are transferred as one packet to at least one client by the communication controller.

Computer network system for packet-transferring data between computers,

A synchronizing circuit including a plurality of latches, comprised of a first dynamic type through latch circuit and a second dynamic type through latch circuit between which is disposed a static type through latch circuit, the circuits connected in cascade. Data is sampled at the timing of the rising edge of the clock signal generated by a pulse generation circuit connected to a clock input circuit and data is output at the timing of the trailing edge. By defining the clock pulse width generated at the pulse generation circuit larger than the clock skew, it is possible to prevent malfunctions of the LSI caused by clock skew caused by deviation of timing of the clock distribution. Moreover, by providing a dynamic type through circuit for a scan test input to the first dynamic type through latch circuit in parallel, a scanning function can be realized and a malfunction due to the clock skew during scanning can be prevented.

Synchronizing circuit with dynamic and static latch circuitry

An object of the present invention is to provide an embedded testing circuit of a dual port memory capable of effectively testing the memory using a short test pattern while making simultaneous write/read from both of the ports. The testing circuit comprises an address inputting circuit selectively supplying M-sequence pattern data or their inverted pattern data to scan registers on the port A at the address input side and also selectively supplying pattern data in inverse relationship to the pattern data supplied to the port A to scan registers on the port B and a data inputting circuit selectively supplying the M-sequence pattern data or their inverted pattern data passed through the scan registers on the port A at the address input side to scan registers on the port A at the data input side and also selectively supplying the inverted pattern data or the M-sequence pattern data passed through the scan registers on the port B at the address input side to scan registers on the port B at the data input side.

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Kawasaki, Japan

Takeshi Onodera