Adv Antest Corporation

Mitsubishi Gas Chemical Company, Inc.

Mgc Filsheet Co., Ltd.

Takeshi Onishi

Osamu Kakinoki

Hiroki Ikeda

Katsuhiko Suzuki

Yoshihito Kobayashi

Shotaro Ohno

Shin Nemoto

Hidetaka Shimizu

Toshinari Aoki

Masahide Takeda

Yasuyoshi Nakayasu

Hirohiko Aikawa

Kosei Hino

Hiroo Nakamura

Katuhiko Suzuki

Katsumi Kojima

Kishin Ozawa

Tadashi Kainuma

Masataka Sugiyama

Shohei Takahagi

Minoru Yatsuda

Hidetaka Nakazawa

Yamada Naruhito

Tanaka Koichi

Bannai Kuniaki

Provided is a polymer film which can eliminate both moire and glitter and is suitable for use as a diffusion film. The above-mentioned problems are solved with a polymer film, a surface of which has an arithmetic average roughness Ra of 0.63-1.80 &#x3bc;m, a root mean square roughness Rq of 0.76-2.40 &#x3bc;m, and an average height Rc of roughness-curve elements of 2.45-7.20 &#x3bc;m.

Polymer film, and light diffusion film comprising same for display

A synthetic resin laminate is excellent in shape stability in high-temperature high-humidity environments and in surface hardness and usable for a transparent substrate material or protection material. A synthetic resin laminate includes a substrate layer containing a polycarbonate (B); and a resin layer laminated on one or both surfaces of the substrate layer, the resin layer containing a resin (A) that contains a (meth)acrylate copolymer (a1) and a polycarbonate (a2); wherein (a1) is a (meth)acrylate copolymer composed of 5 to 80% by mass of an aromatic (meth)acrylate unit (a11) and 20 to 95% by mass of a methyl methacrylate unit (a12); (a2) is a polycarbonate containing a constituent unit represented by formula [1]; and the ratio of (a1) with respect to the resin (A) is 5 to 55% by mass, and the ratio of (a2) with respect to the resin (A) is 95 to 45% by mass.

Synthetic resin laminate

An optical sheet is formed by laminating, by co-extrusion molding, a first layer containing a polycarbonate resin, a second layer containing a polyamide resin, and a third layer, wherein the second layer is laminated between the first layer and the third layer, the first layer and second layer, and the second layer and third layer can each be peeled at the interface, and the outer surface of the first layer has a fine grooved structure. The optical sheet, which is provided with a plurality of layers in such a way, is capable of retaining, a sufficient amount of heat in a laminate in a mold since the entire sheet can be made thick during melt extrusion molding, and is able to improve the transferability of the fine grooved structure. In addition, the optical sheet can be made thinner by using only the peeled first layer as an optical sheet.

Optical sheet and method for manufacturing same

The present invention has an object of providing a synthetic resin laminate that is excellent in shape stability against a high temperature and high humidity environment, surface hardness and the like. The above object is achieved by a synthetic resin laminate, comprising a substrate layer (B) containing polycarbonate; and a resin layer (A) laminated on one or both of two surfaces of the resin layer (B), the resin layer (A) containing 5 to 55% by mass of (meth)acrylate copolymer (C) and 95 to 45% by mass of polycarbonate (D), wherein the (meth)acrylate copolymer (C) contains an aromatic (meth)acrylate unit (c1) and a methyl methacrylate unit (c2) at a mass ratio (c1/c2) of 5-80/20-95, and the (meth)acrylate copolymer (C) has a mass-average molecular weight of 5,000 to 30,000; and the polycarbonate (D) has a mass-average molecular weight of 21,000 to 40,000.

The present invention provides a synthetic resin laminate, which is excellent in terms of shape stability in a high-temperature or high-humidity environment, surface hardness, heat resistance, coating adhesion and the like. The synthetic resin laminate is formed by laminating a resin layer (A) including 5% to 55% by mass of a (meth)acrylate copolymer (C) and 95% to 45% by mass of a polycarbonate (D) on one surface or both surfaces of a base material layer (B) comprising polycarbonate, wherein the synthetic resin laminate is characterized: in that the (meth)acrylate copolymer (C) includes an aromatic (meth)acrylate unit (c1) and a methyl methacrylate unit (c2) at a mass ratio (c1/c2) of 5 to 80/20 to 95; in that the mass average molecular weight of the (meth)acrylate copolymer (C) is 5,000 to 30,000; and in that the viscosity average molecular weight of the polycarbonate (D) is 21,000 to 40,000.

The present invention has an object of providing a synthetic resin laminate that is usable for a transparent substrate material or protective material, has high thermoformability (pressure formability, thermal-bending formability), high insert moldability, and high surface hardness and/or impact resistance, and also providing a molded body formed by molding such a synthetic resin laminate. The synthetic resin laminate includes a polycarbonate-based substrate layer; and a resin laminated on one of, or both of, two surfaces of the polycarbonate-based substrate layer, the resin containing a specific (meth)acrylate copolymer resin and a specific polycarbonate resin. The polycarbonate-based substrate layer includes a polymer alloy and thus has a glass transition temperature (Tg) of 110 to 130&#xb0; C. Thus, the resultant synthetic resin laminate has high thermoformability and high surface hardness.

A semiconductor device testing system is provided which can efficiently utilize a plurality of semiconductor device testing apparatus. There are provided a host computer for controlling a plurality of semiconductor device testing apparatus A, B, and C, and a dedicated classifying machine Storage information memory means for storing storage information of each semiconductor device such as a number assigned to each tested semiconductor device, the test results of each semiconductor device, and the like is provided in the host computer Without sorting the tested devices or with the sorting operation of the tested devices into only two categories in the handler part of each testing apparatus, the tested devices are transferred from the test tray to a general-purpose tray, and during this transfer operation, the storage information of each device is stored in the storage information memory means. When all the tests are completed, the storage information of each device stored in the storage information memory means is transmitted to the dedicated classifying machine by which the tested devices are sorted out.

Semiconductor device testing apparatus and semiconductor device testing system having a plurality of semiconductor device testing apparatus

In an IC tester comprising a tester part and a handler which includes two test stations or an IC tester comprising a tester part and two handlers, useless waiting times wasted by the tester part are eliminated. Means (SO) is provided for inputting a simultaneous measurement mode into the handler,, and when the simultaneous measurement mode is inputted, the handler waits, in case the test preparation in the first test station,is completed and the test preparation in the second test station,is not completed, till the test preparation in the second station is completed, and when the test preparation in the second station is completed, the handler transmits the test preparation complete signals of both the stations to the tester part,. The handler waits, in case the test preparation in the second station is completed and the test preparation in the first station is not completed, till the test preparation in the first station is completed, and when the test preparation in the first station is completed, the handler transmits the test preparation complete signals of both the stations to the tester part.

Semiconductor device tester

In an integrated-circuit tester which is provided with a contact failure analysis/storage part for counting and storing the number of failures occurring at each contact, an automatic stop part for deciding contact as defective based on the numbers of failures stored in the storage part and for stopping a handler, an automatic turn-OFF part by which, upon each operation of the automatic stop part, contacts having met the stop condition are automatically put in their unused state, and a defective contact display for displaying the number of contacts put in the unused state upon each automatic stop of the handler, an operator checks the number of contacts put in the unused state upon each automatic stop of the handler, then decides whether or not all the contacts used are to be replaced, and performs the necessary operations for resuming the test.

IC tester simultaneously testing plural ICS

An IC testing apparatus in which an accident occurring when a measurement part mounted on a test head is changed can be avoided. A type signal generating device,is provided on each of measurement parts so that a type signal TYPE can be sent from the type signal generating device,when a measurement part,is mounted on a test head,. The type signal is read by a type signal reading device,provided in an IC tester,. The type signal is transmitted to a handler,together with the number of simultaneous tests SUM extracted from a test program loaded in a main controller,of the IC tester. In the handler, a decision device,determines, based on the transmitted number of simultaneous tests and the type signal, whether or not the test program is proper and whether or not the arrangement of IC sockets set in the handler coincides with the arrangement of IC sockets of the measurement part. A start/stop controller,provided in the IC tester generates a start instruction to start a test when all of the decision results are &ldquo;good&rdquo;, or generates a stop-of-start instruction to prevent the IC tester from starting when even one of the decision results is &ldquo;no-good&rdquo;.

IC testing apparatus

An IC testing method is disclosed in which IC's to be tested are placed on IC carriers disposed in an m-row, n-column array on a test tray in a loader, and the IC's to be tested are connected to sockets disposed as an m-row, k-column array on a socket attachment in a manner corresponding to every a-th column of the IC carriers in a testing section for purpose of measurement. n and k are integers equal to or greater than two, n=ak where a is an integer equal to or greater than two. The IC testing method comprises the steps of determining if the number of IC's to be tested which are present in the loader is greater than the number of IC carriers, if it is determined that the number of IC's to be tested is equal to or greater than the number of IC carriers, causing the loader to load the IC's to be tested on all the IC carriers on the test tray, and causing the test section to connect the loaded IC's to be tested which are located in k columns corresponding to every a-th column of the IC carriers with the corresponding sockets to perform a test of simultaneous measurement and to repeat the test a times while translating the test tray by an IC carrier array pitch, thus completing the testing of all the IC's to be tested on the test tray. If it is determined that the number of IC's to be tested is less than the number of IC carriers, the IC's to be tested are disposed at respective positions in a sequence of columns which are subject to a simultaneous measurement in the test section, and the IC's to be tested in every a-th column of the IC carriers are connected with the corresponding sockets to perform a test of simultaneous measurement in the test section, and such test is repeated while translating the test tray by an IC carrier array pitch.

IC testing method

Semiconductor device testing apparatus and semiconductor device testing

A semiconductor device testing apparatus in which ICs to be tested are loaded on a test tray in a loader section, the test tray is transported into a test section to test the ICs, after the completion of the test, the tested ICs on the test tray are transferred from the test tray onto a general-purpose tray in an unloader section, the test tray which has been emptied of the tested ICs is transported to the loader section, and the above operation is repeated, and which can detect a failure of an IC carrier mounted to the test tray independently of detection of a failure IC socket is provided. An IC carrier failure analysis memory is provided which has storage addresses the number of which is equal to the number of IC carriers mounted to each of the test trays, and the number of ICs as determined to be defective is stored and accumulated in each of the storage addresses of the IC carrier failure analysis memory. When the accumulated value exceeds a setting value, a decision is rendered that the associated IC carrier on which the ICs as determined to be defective have been loaded is defective.

Growing community of inventors

Tokyo, Japan

Takeshi Onishi