Mitsubishi Denki Kabushiki Kaisha

Takeshi Noguchi

Shigeru Harada

Atsushi Hachisuka

Yoshihiro Hirata

Junichi Arima

Reiji Tamaki

Kenji Saitoh

Kazuaki Miyata

Hiroshi Mochizuki

Eisuke Tanaka

Masanori Obata

Source/drain regions of an MOS transistor are formed at a surface of a p-type silicon substrate. A storage node electrically connected to the source/drain regions penetrates a bit line to reach the n-type source/drain region. The storage node and the bit line are insulated from each other by a sidewall insulating layer. Thus, a semiconductor memory device suitable for high integration is obtained in which short-circuit between the storage node and the bit line on a gate electrode layer can be prevented.

Method of making a semiconductor device with sidewall insulating layers in the capacitor contact hole

Semiconductor device with sidewall insulating layers in the capacitor

A semiconductor memory device comprises a plurality of memory cells, and each of the memory cells includes a transistor region in which one or more transistors included in the memory cell are formed and a high-resistance element region in a resistor layer overlying the transistor region in which one or more high-resistance elements are formed. The high-resistance element region has a shape different from that of the transistor region and occupies an area not larger than that of the transistor region.

Semiconductor memory device comprising one or more high-resistance

A semiconductor integrated circuit which is of entire microstructure so as to reduce a gate length as to an EPROM formed on a substrate, thereby increasing the quantity of a current flowing between a source and a drain and, on the other hand, a transistor portion other than the EPROM on the same substrate is of structure for weakening the electric field between the source region and the drain region by means of the LDD technique or the like, thereby preventing the occurrence of a breakdown in the channel caused by hot electrons.

EPROM IC having reduced impurity regions

An Al layer (6) is first formed to cover an opening region (9) for interconnection in a semiconductor device. Then, an Al-Si-Ti layer (7) having a higher degree of hardness than that of the Al layer (6) is formed on the Al layer (6) and subsequently a mixture layer (8) of aluminum hydrate and aluminum oxide is formed on the surface of the Al-Si-Ti layer (7). Thus, a multilayered film of electrode and interconnection (11) is formed.

Semiconductor device and method of manufacturing thereof

An apparatus for forming a thin film on a substrate has a first reaction chamber in which a thin film is formed by gaseous discharge and a second reaction chamber in which reactive atoms are generated. The first and second reaction chambers commuicate with one another through an orifice in the first reaction chamber. The first reaction chamber houses a device for generating a film on a substrate, and the second reaction chamber houses a device for generating reactive atoms. The orifice is disposed in the vicinity of both a film-forming region in the first reaction chamber and a reactive atom-generating region in the second reaction chamber so that reactive atoms from the second reaction chamber will pass through the orifice and enter the film-forming region in the first reaction chamber, combine with particles in the film-forming region to form a chemical compound, and accumulate on the substrate. In preferred embodiments, the reaction chambers are formed by a single housing having a partition which has an orifice therein and which divides the housing into two reaction chambers.

Apparatus for forming a thin film

The rough ground rear surface 13b of a semiconductor wafer 11 is mirror-polished by localized irradiation with a focused laser beam 21. The wafer is moved relative to the beam, and the melt puddle formed by the beam thereafter recrystallizes at its trailing edge 24 to leave a mirror smooth rear surface 13c.

Growing community of inventors

Hyogo, Japan

Takeshi Noguchi