Sony Corporation

Fujitsu Corporation

Takeshi Ninomiya

Jun Takayama

Tadao Fujita

Yoshiaki Inaba

Takashi Watanabe

Kiyosuke Suzuki

Hideto Suzuki

Yoshikazu Kurose

Masaaki Sakai

Toshiya Nakajima

Akihiro Iseno

Shinji Hamada

Madoka Ichikawa

Chiaki Yamauchi

Daijiro Okihara

Junichi Yoshioka

A storage apparatus which performs writing and reading of data on a magnetic tape by the helical scan method using a rotary head, in particular one suited to use with a large-sized host computer, which storage apparatus includes mainly a storage control unit connected to the host computer and a drive unit for reading from and writing on the magnetic tape. System areas are formed on the magnetic tapes, which system areas have tables which include management information relating to the magnetic tapes themselves and able to be renewed by the storage control unit. By using these tables, the magnetic tapes can be easily accessed at a high speed, diagnosed as to trouble, and managed in data blocks.

Magnetic-tape storage apparatus

Sampling rate converting apparatus

In a sampling rate converter, an input digital video signal has its sampling rate converted from a first sampling frequency to a second or different sampling frequency by oversampling the input digital video signal at a rate which is an integral multiple of the first sampling frequency so as to generate zero values between data of the input digital video signal, interpolating an output signal from the oversampled input digital video signal, decimating the interpolated output signal for generating therefrom a digital video signal having the desired second sampling frequency, and only then applying the digital video signal having the second sampling frequency to a low pass filter, preferably of the finite impulse response type, for eliminating therefrom an undesirable signal component which is due to the sample rate conversion and which appears between frequency bands of one-half of the first and second sampling frequencies, respectively.

Sampling rate converter

In a method and apparatus for encoding and decoding data in the residue number system, input binary data are supplied to an encoder to be divided by moduli m.sub.0, m.sub.1, m.sub.2, . . . m (i.e., positive integers having a mutually prime relation). Residue data corresponding to respective moduli are output from the encoder to a digital filter circuit including a plurality of digital filters, each filter corresponding to a respective modulus. Processing for some specified application is performed by the digital filters based, for example, on the Mixed Radix Conversion Method method to generate output data still in the residue format. The residue data output from the digital filters then are input to a decoder to be converted back into binary data. Encoding is performed by splitting n-bit straight binary data into, for example, upper bit data and lower bit data, received by respective ROM tables. Each ROM table outputs a value to another common ROM table which outputs the converted residue data. The ROM tables convert the binary data by weighing each input bit by a value corresponding to the particular bit. The capacity needed for the ROM tables is reduced, enabling the encoder circuit configuration to be simple and fast. Decoding is performed by scaling down RNS data to obtain a plurality of residue data corresponding to respective moduli, adding one to a fixed bit of the residue data for discriminating positive and negative numbers, and performing addition on such residue data with fixed moduli to obtain binary data.

Method and apparatus for encoding and decoding data in residue number

A relatively simplified sampling frequency converter for use in a format conversion apparatus is operative to convert sampled input data of an input sampling frequency into sampled output data of an output sampling frequency. The converter has an over-sampling circuit for increasing the sampling frequency of the sampled input data by a predetermined factor or coefficient to provide over-sampled data; an output data extractor for periodically extracting data from the over-sampled data in response to a timing pulse having the output sampling frequency; and a controller for controlling the phase of the timing pulse which controls the phase of the sampled output data.

Sampling frequency converter

A recording apparatus includes a memory circuit for storing a video signal derived from a high speed scanning video camera the scanning speed of which is faster than the scanning speed of a standard television signal and a plurality of rotating magnetic heads supplied with video signals of a plurality of channels which are read out in parallel from the memory circuit. The video signals of the plurality of channels are recorded on a magnetic tape by the plurality of rotating magnetic heads so as to sequentially form slant adjoining tracks.

Recording apparatus for recording a video signal obtained from a high

An automatic offset compensating bipolar A/D converter circuit includes an A/D converter and a feedback circuit, which automatically compensates offset error between a specific level of input having analog voltage and a specific output code of output digital value corresponding to that input analog voltage. The A/D converter can convert the input analog voltage, which includes residual noises more than 1 LSB, into an output digital value. The feedback circuit can add a compensation voltage to the input analog voltage so as to equalize the posibilities of occurrence of codes which are more than and less than a specific output code of an output digital value to each other in accordance with an output digital value.

Automatic offset compensating bipolar A/D converter circuit

Magnetic recording and reproducing apparatus records and reproduces on or from a magnetic recording tape a high speed video signal obtained from a high speed scanning video camera having a scanning speed N times the scanning speed of a standard video camera generating a standard television video signal, where N is an integer. The apparatus includes a drive for driving the magnetic recording tape to a run at tape speed N times the tape speed of a standard recording apparatus, circuitry for dividing the high speed video signal into N-channel video signals, and an expander for expanding the time axis of the high speed video signal so that each of the N-channel video signals is slightly compressed as compared to the standard television video signal. A modulator modulates each of the video signals the time axes of which are expanded, and a recording and reproducing mechanism includes a rotary drum having N rotary magnetic heads mounted on the circumference thereof with an equal angular distance therebetween to record each of the modulated video signals on the magnetic recording tape as successive tracks and a playback head mounted on the circumference at a predetermined position. The diameter of the rotary drum is in a predetermined relation to that of the standard magnetic recording and reproducing apparatus.

Magnetic recording and reproducing apparatus for recording and

Velocity error control apparatus for use in a video signal time base corrector of the type including a main memory having addressable storage locations for storing successive lines of video signals, write-in circuitry including a write-in clock signal generator synchronized with time base errors in the video signal for writing successive lines of video signals into addressed storage locations at a write-in clock signal rate, and read-out circuitry including a controllable read-out clock signal generator for reading out successive lines of video signals from addressed storage locations at a substantially constant read-out clock rate. The velocity error control apparatus includes a velocity error detector for detecting velocity errors in successive lines of the video signals which are written into the main memory. A velocity error store has a plurality of storage locations, each being operative to store a velocity error signal representing the velocity error of an associated line of video signals, and a velocity error read-out circuit reads out the velocity error signal from the velocity error store, which velocity error signal is associated with a line of video signals when the associated line of video signals is read out from the main memory. A modifying circuit modifies the read out velocity error signal as a function of at least one velocity error signal which is associated with at least one adjacent line of video signals. The modified velocity error signal is used to modulate the read-out clock signals so as to compensate for the velocity errors in successive lines of video signals.

Velocity error control apparatus

In an analog to digital converter in which each sampled portion of an incoming video or other analog signal is converted to a digital character in a plurality of parallel conversions occurring serially; the range of the voltage level reference signals of descending magnitude which are applied to comparators for effecting a relatively fine parallel conversion of a sampled analog signal is selected to be larger than, and offset in respect, to the steps or increments of the voltage level reference signals of descending magnitude which are applied to comparators for effecting a preceding relatively coarser parallel conversion, and the encoded outputs from the serially occurring parallel conversions are digitally added with the least significant bit of the encoded output from each preceding relatively coarser parallel conversion being accorded the same weight as the most significant bit of the encoded output from the next following relatively finer parallel conversion so as to eliminate from the result of the digital addition defects that would otherwise arise from inaccuracies in the voltage level reference signals and/or in the comparing operations of the comparators.

Parallel-serial analog to digital converters

In a time base corrector which converts incoming video signals to digital form and writes the digitized signals in sequentially enabled units of a main memory at a clocking rate varying generally in accordance with time base errors in the incoming signals, whereupon the signals temporarily stored in the memory are read out or fetched from the successive main memory units at a clocking rate which is standard at least at the beginning and end of each line interval and the read out signals are reconverted to analog form for eliminating the time base errors: the clocking rate for reading out the video signals from each of the main memory units is modulated during each line interval in accordance with velocity error information stored in a velocity error memory during writing of such video signals in the respective main memory unit.

Video time base corrector

In a time base corrector which converts incoming video signals to digital form and writes the digitized signals in a memory at a clocking rate varying generally in accordance with time base errors in the incoming signals, whereupon the signals temporarily stored in the memory are read out or fetched therefrom at a standard clocking rate and reconverted to analog form for eliminating the time base errors; the memory is composed of a plurality of cyclically enabled memory units which each have a capacity to store an even number of line intervals of the video signals.

In a time base corrector which converts incoming video signals to digital form and writes the digitized signals in a memory at a clocking rate varying in accordance with time base errors in the incoming signals, whereupon the signals temporarily stored in the memory are read out or fetched therefrom at a standard clocking rate and reconverted to analog form for eliminating the time base errors; the clocking rate for storing the digitized signals is determined by a write clock pulse signal generator having an automatic frequency control circuit in which the output frequency of a variable frequency oscillator is varied in dependence on the horizontal synchronizing signals in the incoming video signals, and an automatic phase control circuit in which the output of the variable frequency oscillator is phase shifted in dependence on the burst signals separated from the incoming video signals.

Write clock pulse signal generator for digital time base corrector

In a time base corrector which converts incoming video signals to digital form and writes the digitized signals in sequentially enabled units of a main memory at a clocking rate varying generally in accordance with time base errors in the incoming signals, whereupon the signals temporarily stored in the memory are read out or fetched from the successive main memory units at a standard clocking rate and reconverted to analog form for eliminating the time base errors: a drop-out memory stores drop-out information in respect to drop-outs detected in the incoming video signals written in each of the main memory units; drop-outs are eliminated in the output from the time base corrector by rewriting, in each memory unit storing video signals having drop-out as indicated by the drop-out memory, video signals from another memory unit shown by the drop-out memory to be free of drop-out, with such rewriting being effected simultaneously with the read out of the video signals from such other memory unit; and upon the rewriting of video signals in a memory unit, the stored drop-out indicating information in respect to that memory unit is erased from the drop-out memory. Further, the clocking rate for reading out the video signals from each of the main memory units is modulated in accordance with velocity error information stored in a velocity error memory during writing of such video signals in the respective main memory unit, and the velocity error memory is operative, upon rewriting in a main memory unit for eliminating drop-out, to replace the velocity error information stored in respect to such main memory unit with the velocity error information associated with the main memory unit from which the rewritten video signals are drawn.

A novel circuit is provided for controlling an alternating current supplied to a load which includes a variable impedance element in the form of a low emitter concentration transistor which is bidirectional, and which has a high gain. The impedance of the variable impedance element to the flow of current therethrough is substantially the same in either direction of current flow.

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Kanagawa, Japan

Takeshi Ninomiya