Hitachi, Ltd.

Hitachi Process Computer Engineering, Inc.

Other

Takeshi Miyao

Tomoaki Nakamura

Shigenori Kaneko

Hiromitsu Kato

Saburou Iijima

Nobuyasu Kanekawa

Katsumi Kawano

Yoshiki Kobayashi

Shigetoshi Sameshima

Masayuki Tanji

Hiroaki Fukumaru

Koji Masui

Manabu Araoka

Katsunori Tagiri

Shinichiro Kanekawa

Toshihiko Nakano

Hiroshi Wataya

Ryokichi Yoshizawa

Yasuo Sekine

Hidebumi Miyata

An object of the invention is to save the trouble of mapping sensor chips on a map information system. A map information management unitis accessed via a network. Neighborhood information based on a present position measured by an own position measuring unitis obtained by searching a map DB. A sensor information setting unitdisplays the neighborhood information in a display unit. An ID reading unitreads an IDof a sensor chip, and registers the IDin the map DBafter associating it with equipment information displayed in the display unit. The measurement values measured by a sensorare transmitted from an antenna 114 and received by a sensor information receiving unitof the receiver. A sensor information communication unitaccesses the networkand the measurements are transmitted to a sensor information management unit. The measurement values are accumulated in a sensor DB. The sensor DBis searched using a sensor ID associated in the map DBand the measurements are viewed as map information associated with equipment.

Sensor network system

In providing services in an environment in which apparatuses constituting a system change dynamically, flexible control of access control is performed for the apparatuses whose access rights and service providing policies are different or have not been set beforehand. In a distributed system where computers each having a function of storing data and processing a program and a communication facility perform data exchange through a communication medium, and thereby perform processing, control of limiting an access to the system etc. is performed as a shared session that is established by synthesizing access rights and service providing policies owned by the apparatuses, and accesses to the apparatuses and provision of services are performed through the shared session, whereby the access rights and the services to be provided are controlled according to a configuration of apparatuses constituting the system.

Access restriction control device and method

A system allows a user to select a service on a device and request a service executing function of a server to carry out the service. An authentication function authenticates the user and searches the functions of devices required in the requested service within the authority given to the user. The function acquires and registers the right to use in a device-configuration managing function through a right-to-use managing function. An adaptor delivering function delivers specifications for setting connections between functions required for execution of the service and a group encryption key generated by a key-generating function to devices. Device coordinating functions set device-embedded functions based on the received specifications. The functions conduct cipher communication with other devices using the key and carry out the service.

Service executing method and service providing system

A computer system has a plurality of processing units (,-,-,-n) connected via one or more system buses (,-,-,). Each processing unit (,-,-,-n) has three or more processors (,-,-,-,) on a common support board (PL) and controlled by a common clock unit (,). The three processors (,-,-,-,) perform the same operation and a fault in a processor (,-,-,-,) is detected by comparison of the operations of the three processors (,-,-,-,). If one processor (,-,-,-,) fails, the operation can continue in the other two processors (,-,-,-,) of the processing unit (,-,-,-n), at least temporarily, before replacement of the entire processing unit (,-,-,-n). Furthermore, the processing unit (,-,-,-n) may have a plurality of clocks (A,B) within the clock unit (,), with a switching arrangement so that the processors (,-,-,-n) normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories (,) may be connected in common to the processors (,-,-,-,), so that failure of one cache memory (,) permits the processing unit (,-,-,-n) to continue to operate using the other cache memory (,). Coherence of the contents of the cache memories (,) may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory (,-,-,-,) of a processor (,-,-,-,) which differs from that in the external cache memory (,). Coherence of protocols may also ensure that data in caches (,) of the different processor units (,-,-,-n) are always correct.

Processing unit for a computer and a computer system incorporating such a processing unit

A computer system has a plurality of processing units connected via one or more system buses. Each processing unit has three or more processors on a common support board (PL) and controlled by a common clock unit. The three processors perform the same operation and a fault in a processor is detected by comparison of the operations of the three processors. If one processor fails, the operation can continue in the other two processors of the processing unit, at least temporarily, before replacement of the entire processing unit. Furthermore, the processing unit may have a plurality of clocks (A,B) within the clock unit, with a switching arrangement so that the processors normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories may be connected in common to the processors, so that failure of one cache memory permits the processing unit to continue to operate using the other cache memory. Coherence of the contents of the cache memories may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory of a processor which differs from that in the external cache memory. Coherence of protocols may also ensure that data in caches of the different processor units are always correct.

Processing unit for a computer and a computer system incorporating such

A computer system and method for enabling memory expansion without shutting off the computer system are disclosed. The computer system has a dual memory configuration and supports memory insertion and extraction while being on-line. The memory content of one system may be copied to the memory of another system according to a predetermined priority or after a predetermined delay. Memory may be used efficiently during the insertion or extraction by securing a status management table expansion area in an expanded portion of memory. Memory may be expanded in computer systems that do not have an open memory slot by replacing the installed memory with a memory having a larger capacity.

Computer system including a dual memory configuration which supports

A program replacing method is provided for an uninterruptible online computer system. The computer system includes an auxiliary storage unit for storing a program currently running in the computer system and another program to replace the current running program and a replacement request managing table for storing replacement requests and program IDs of such replacing programs. These programs include checkpoints pre-programmed at selected locations therein. At an optional checkpoint, the replacement request managing table is retrieved for checking whether or not the replacement is requested. If a replacement is requested, the new program is started according to the program ID and the current program is terminated.

Method and system for replacing program in uninterruptible computer

Growing community of inventors

Hitachioota, Japan

Takeshi Miyao