Nippon Gakki Seizo Kabushiki Kaisha

Suzuki Motor Corporation

Takeshi Matsuyama

Takashi Yoshida

Takayuki Kodaka

Tamaki Kuki

Masatoshi Kimpara

Terumoto Nonaka

Masao Kosugi

Madoka Suzuki

A tiller handle includes: a throttle shaft including first shaft and the second shaft; a conversion mechanism configured to convert rotation of the first shaft into a rectilinear motion of the throttle cable; an engagement pin provided in the second shaft; and a restriction member (shift arm) engaged with the engagement pin depending on a position of a selector in synchronization with the selector to restrict rotation of the second shaft in a throttle valve open direction. The first shaft and the second shaft are configured to relatively rotate each other only by a predetermined angle.

Steering handle of outboard motor

A vertical or horizontal type junction FET including a channel-gate structure formed by a double diffusion process in which two treatments for diffusing different impurities are executed through an identical opening provided in a diffusion mask. For fabricating a vertical type junction FET, such double diffusion process is applied to stacked upper and lower semi-conductor layers having opposite conducting types thereby forming a channel region adjacent to the upper semi-conductor layer which functions as a first gate region and forming a second gate region adjacent to the channel region and remote from the first gate region. For fabricating horizontal type junction FET, the double diffusion process stated above is applied to a single semi-conductor layer to form a first gate region thereby forming a channel region adjacent to the first gate region and a second gate region adjacent to the channel region and remote from the first gate region. In either type of junction FET's the width of each channel region is precisely determined and corresponds to the difference in the diffusion depths in the two diffusion treatments. Moreover, the impurity concentration and the concentration profile of each channel region is determined independently of those of the drain or source region. Furthermore in the manufacturing process of each FET, the second gate region is self aligned so as to overlap a corresponding channel region.

Junction field effect transistor

In an integrated injection logic (IIL) type semiconductor integrated circuit, an injector transistor is formed with a field effect transistor (FET) and an inverter transistor is formed with a bipolar transistor (BPT). The drain region of the FET is merged into the base region of the BPT. The base of the BPT constitutes a logic input and the collector of the BPT constitutes a logic output. The FET may be either of the junction type or of the insulated gate type. The carrier injection efficiency can be improved to approximately unity over a wide range of the injection current.

IIL Type semiconductor integrated circuit

Method of manufacturing junction field effect transistors

A horizontal junction-type field effect transistor having a saturated drain current to drain voltage characteristic and constituting an input transistor and a vertical junction-type field effect transistor having an unsaturated drain current to drain voltage characteristic and constituting an output transistor are connected in cascode fashion to compose a compound field effect transistor. This compound field effect transistor has a saturated characteristic, a high transconductance gm and a high breakdown voltage resembling those of a pentode vacuum tube. This compound field effect transistor is constructed in the form of monolithic integrated circuitry by the combined use of the dielectric isolation technique utilizing mesa groove and the pn-junction isolation technique.

Compound field effect transistor

A field effect transistor having unsaturated characteristics comprising a plurality of current channels consisting of a semiconductor material of an impurity concentration between 1 .times. 10.sup.13 to 1 .times. 10.sup.15 atoms/c.c., each current channel having a minimum diameter between 2 and 15 .mu.m so that the depletion layer growing from the gate junction nearly but not perfectly closes the current channel at zero gate bias. This junction type field effect transistor provides unsaturated and well aligned parallel characteristic curves and reduces power loss as compared to conventional unsaturated type vertical field effect transistors.

Growing community of inventors

Hamamatsu, Japan

Takeshi Matsuyama