Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Takeshi Kodaka

Akira Takeda

Nobuhiro Nonogaki

Hiroaki Tanaka

Yutaka Yamada

Akira Yokosawa

According to one embodiment, a virtualization support device includes: a first processor controlling an operation of accelerators; a memory holding first information regarding a first application executed by a second processor, second information regarding a second application executed by the second processor, one or more first requests from the first application, and one or more second requests from the second application; and a management unit coupled to the first processor and the memory. The first processor performs arbitration of an order in which the accelerators execute the first and second requests, controls setting of the management unit by using the one of first and second information based on the arbitration, and causes the accelerators to execute one of the first and second requests based on the arbitration.

Virtualization support device, control method of virtualization support device, and calculation system

A sensor data collecting device includes a first circuit and a controller. The controller has a first state and a second state and acquires data of one or a plurality of sensors in the second state. The first circuit includes a first register and causes the controller to transit from the first state to the second state. The controller sets the first register based on a minimal data generation period among data generation periods.

Sensor data collecting device

According to one embodiment, a multiprocessor system includes a plurality of processors, a power supply device and a shared memory. The shared memory includes a thread pool and a thread queue. In the thread pool, threads each having waiting events are registered in association with the numbers of the waiting events. In the thread queue, threads having no waiting event are registered. One or more first processors acquire first thread from the thread queue and execute the first thread. A second processor updates the number of waiting events of a second thread, which is registered in the thread pool, having completion of required procedure for the second thread by the first thread as a waiting event. A third processor operates supply of power to the first processors individually based on the number of threads in the thread queue and the number of waiting events.

Multiprocessor system and method of controlling power

A fixed length memory block management apparatus has a plurality of processors which execute applications, a memory which is shared by the plurality of processors, an application program, an initialization program, and an access right allocation program being stored in the memory. The apparatus has an application execution unit which starts up the application program to execute the application, an initialization unit which starts up the initialization program to set a memory block management area including a plurality of sub-blocks at the memory, and an access right allocation unit which starts up the access right allocation program to allocate an access right of a memory block of the sub-block set by the initialization unit to the application execution unit.

Fixed length memory block management apparatus and method for enhancing memory usability and processing efficiency

According to one embodiment, a state manager classifies an area allocated to the multi-core processor in a first memory area into one of a first state in which allocation to processor cores is not performed, a second state in which allocation to one of the processor cores is performed and read and write are performed, and a third state in which allocation to one or more of the processor cores is performed and read and write are prohibited, and further performs a transition from one of the first state, the second state, and the third state to another. A cache/memory manager writes back a corresponding cache when the state manager performs the transition from the second state to the third state.

Multi-core processor system and multi-core processor

An image processing apparatus has a memory in which a plurality of image processing commands are stored, a dependent information producing unit which produces dependent information in each image data block becoming a target image processing, the dependent information indicating a dependency relationship between image processing of the image data block and another processing, a dependency relationship solving unit which makes a determination of a practicable image processing based on the dependent information, the dependency relationship solving unit writing an image processing command of the practicable image processing in the memory, and a plurality of image processing units which read an image processing command stored in the memory, the image processing units performing the image processing to the image data block based on the image processing command.

Image processing apparatus, image processing method, and computer-readable storage medium

In a multiprocessor system including a plurality of processors, the processors execute, at a time of migration a task operating in own processor to another processor, a transmitting task for transmitting the migration target task to a destination processor, and when an interrupt request to be received and executed by an interrupt handler accompanying the migration target task is generated during transmission of the migration target task, the transmitting task receives the interrupt request instead of the interrupt handler and starts the interrupt handler.

Multiprocessor system and computer program product

A memory management system includes a plurality of processors, a shared memory that can be accessed from the plurality of processors, cache memories provided between each processor of the plurality of processors and the shared memory and invalidation or write back of a specified region can be commanded from a program running on a processor. Programs running on each processor invalidate an input data region of a cache memory with an invalidation command immediately before execution of a program as a processing batch, and write back an output data region of a cache memory to the shared memory with a write back command immediately after execution of a program as a processing batch.

Growing community of inventors

Kanagawa, Japan

Takeshi Kodaka