Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Corporation

Renesas Technology Corp.

Takeshi Kitani

Hiroshi Kawashima

Motoshige Igarashi

Masakazu Okada

Shigeru Hasegawa

Yoichiro Tarui

Katsumi Eikyu

Masayoshi Shirahata

Masao Sugiyama

Kazuhiro Morishita

Takeru Matsuoka

According to the present invention, a switching element includes a substrate, a first gate pad formed on the substrate, a second gate pad formed on the substrate, a first resistor portion formed on the substrate, the first resistor portion connecting the first gate pad and the second gate pad to each other, and a cell region formed on the substrate and connected to the first gate pad. Thus, measurement of the gate resistance value and selection from gate resistances of the switching element can be performed after the completion of the gate-resistor-incorporating-type switching element.

Switching element, semiconductor device, and semiconductor device manufacturing method

A silicon carbide semiconductor device of the present invention comprises a silicon carbide drift layer formed on a silicon carbide substrate, a P-type region formed in a surface layer of the silicon carbide drift layer, and a Schottky electrode formed above the silicon carbide drift layer correspondingly to a forming portion of the P-type region. The P-type region is formed of a plurality of unit cells arranged therein. Each of the unit cells has at least a first distribution region in which the P-type impurity is distributed at first concentration and a second distribution region in which the P-type impurity is distributed at second concentration higher than the first concentration. With this structure, it is possible to provide a silicon carbide semiconductor device in which a sufficient breakdown voltage can be achieved with less number of ion implantations.

Silicon carbide semiconductor device

The semiconductor device includes a semiconductor substrate and, in an element isolating region in the semiconductor substrate, a first active area A/A dummy pattern and a second A/A dummy pattern having a pitch smaller than that of the first A/A dummy pattern. Placement of the first A/A dummy pattern and placement of the second A/A dummy pattern are carried out in separate steps. The semiconductor substrate may be divided into a plurality of mesh regions, and a dummy pattern may be placed in each mesh region according to an area of the mesh region being occupied by an element pattern located therein.

Semiconductor device with a first dummy pattern

Semiconductor device with dummy patterns

A semiconductor device with a polycide interconnection including a refractory metal silicide film improved in adherence with an interlayer insulation film, and a method of fabricating such a semiconductor device are provided. The local impurity concentration of a tungsten silicide film in the proximity of the interface between an interlayer oxide film and the tungsten silicide film is set to 5&times;10 atms/cm -2&times;10 atms/cm .

Semiconductor device with multi-layer interconnection

Both P type and N type impurities are implanted from a plurality of directions. The tilt angle &thgr; of the implantation direction against the normal of the main surface of a semiconductor substrate is fixed to 10&deg;, and the deflection angle &phgr; is set to such four directions (X, X&plus;90&deg;, X&plus;180&deg;, and X&plus;270&deg;, where X is an arbitrary angle) that projecting components of a vector indicating the implantation direction are opposed to each other on two lines that cross each other at right angles along the main surface of the semiconductor substrate. Thereby, the dependency of the breakdown voltage of element isolation on the direction of a well boundary is suppressed to realize a high breakdown voltage of element isolation in all directions.

Method of manufacturing semiconductor device

An interlayer film layer is formed on an (N&minus;1)-th interconnection Layer via a barrier film, and an N-th interconnection layer is formed on the interlayer film layer. An interconnection having a Damascene structure is formed in the interconnection layer and the interlayer film layer. The interconnection has an wiring portion having a narrow line width and a pad portion having a wide line width. A recess corresponding to the wiring portion and the pad portion is provided in an insulating film of the interconnection layer. A recess corresponding to the pad portion is provided in an insulating film of the interlayer film layer. A barrier metal and a metal film are deposited in both the recesses, and unnecessary portions of the barrier metal and the metal film are removed by CMP, to form a multilayer interconnection structure.

Growing community of inventors

Tokyo, Japan

Takeshi Kitani