Fujitsu Corporation

Japan Tobacco Inc.

Nrl Pharma, Inc.

Takeshi Kitahara

Kenji Mori

Koshi Koseki

Kunio Ando

Masato Mitsuhashi

Hidenori Watanabe

Masataka Mori

Atsushi Fujihira

Akio Munakata

Susumu Abe

Atsushi Fujihara

Ascochlorin or an analog or derivative thereof and a compound having a primary amino group are mixed and reacted with each other in the presence/absence of a basic catalyst to synthesize a novel imino compound. The novel imino compound thus synthesized is a ligand capable of activating nuclear receptor superfamily such as retinoid orphan receptor (RXR), peroxisome proliferator-activated receptor (PPAR) and steroid receptor (PXR), and shows an effect of promoting the transcription of a drug-metabolizing enzyme CYP7A1. The imino compound has a therapeutic effect on diseases such as lifestyle-related diseases, chronic inflammation and cancers.

Transcriptional factor, process for producing the same and use thereof

The present invention has an object to develop novel compounds which are effective for the therapy of syndrome X, cancer, myxedema, vascular chronic inflammation and the like, and furthermore prevent/treat the restenosis caused in an artery expansion by a balloon or a stent and have the activity facilitating regenerative medicine by inhibiting rejection of own cells or tissues to be transplanted and the method for preparing the same. Novel acetal derivatives obtained by acylating the hydroxyl group at the 2-position of the orcylaldehyde which ascochlorin and its analogs have and thereafter bonding an alcohol to the aldehyde group in the presence of a basic catalyst are found to achieve the object.

Method for preparing novel transcription factors and use

A fetching operation break unit breaks a fetching operation of a block data from a main memory, when a system bus is released during the fetching of the block data and also when data written due to a write access by an external device into the main memory coincides with the fetching of one block data. Further, a notification means notifies the state of the fetching operation to an external cache memory. Therefore, the external cache memory can confirm whether a block-in operation of the microprocessor is broken or not, and the contents of the external cache can correctly coincide with the contents of the internal cache and the main memory by carrying out a steal operation, so that the operational reliability of a computer system can be increased.

Data processing device for maintaining coherency of data stored in main

A comparing unit compares an address of data written into a main memory by an external device with an address of data stored in a cache memory, and a masking unit masks specific bits obtained by a result in said address comparing unit. An invalidating unit invalidates data stored in the cache memory corresponding to the specific bits masked by the masking unit. Therefore, inconsistency between the main memory and the cache memory can be prevented, even when the data are transferred by using a block transfer process.

Data processing device for preventing inconsistency of data stored in

Optically active periplanone-B is manufactured through oxidizing (1RS, 4S, 5E)-isopropyl-7-methylene-5-cyclodecene-1-ol. The oxidized product is regioselectively enolized and then sulfenylated. The sulfenylated product is oxidized and then subjected to decomposition of the sulfoxide. The decomposed product is epoxidated, and the epoxidated product is converted into an enolate which is then oxidized. The oxidized product is oxidized and then regio- and stereoselectively epoxidated to obtain optically active periplanone-B.

Method of manufacturing optically-active periplanone-b

A block access system using a cache memory comprises a first control circuit for producing a block access request for requesting read-out of all data included in a block of a predetermined size in response to an access request from an operation unit and inputting the data read out from a main memory unit into a cache memory, and a second control circuit for reading out data from the main memory unit and sending back to the first control circuit a response signal which indicates any one of execution and cancellation of the requested block access in response to the block access request from the first control means. Memory addresses necessary for reading out all the data in one block are produced by the first control circuit when the block access request is cancelled. Alternatively, memory addresses are supplied by the second control circuit when the block access request is executed.

Block access system using cache memory

4-isopropyl-7-methylene-5-cyclodecen-1-ol

A token-passing type loop transmission system including a plurality of node stations and first and second loop transmission lines, which lines transmit signals in opposite directions. Each node station includes a first and second loop-back circuits and a ring control circuit. The ring control circuit monitors signals passing through the node station, changes end paths in the first and second loop-back circuits to operatively connect the first and second loop transmission lines or to restore the first and second loop transmission lines to a normal state in each loop-back circuit, and transmits a signal on the first or second loop transmission line through the first or second loop-back circuit. By the combination of operations of the node stations, the loop transmission system performs automatic loop configuration control of detection of a fault point therein and constructs a transmission loop line not including the fault point.

Loop transmission system having automatic loop configuration control

An image data conversion method for converting the image data signal to the runlength signal through the process for reading once or several times a runlength code from a runlength conversion table for a given image data signal and a process for adding the pertinent runlength code when the same type of runlength code appears continuously. A character code/character pattern conversion apparatus which uses said image data conversion method, and provides, moreover, a multiplication device for multiplying character enlarging coefficient and the runlength code and a character interval inserting means which adds a character interval width code to the enlarged runlength code and outputs the input character code after converting it to the enlarged character pattern along with the interval code.

Growing community of inventors

Tokyo, Japan

Takeshi Kitahara