Kabushiki Kaisha Toshiba

Takeshi Kitahara

Kimiyoshi Usami

Takashi Ishikawa

Fumihiro Minami

Masahiro Kanazawa

Naoyuki Kawabe

Seiichi Nishio

Masaaki Yamada

Atsushi Masuda

Tetsuaki Utsumi

Toshiyuki Furusawa

Masatoshi Sekine

Hiroaki Nishi

Katsuhiro Seta

Masami Aihara

Kazuyoshi Kohno

Tsutomu Takei

Yoshiki Tsukiboshi

Yusaku Shiro

This disclosure concerns a semiconductor circuit design method for designing a clock wiring structure supplying a clock to a flip-flop by using a computer. The semiconductor circuit design method comprises setting the flip-flop based on circuit information on a semiconductor integrated circuit; obtaining a control signal controlling the flip-flop; calculating a first evaluation value indicating a power consumption and a magnitude of a clock skew time when clock gating is applied to the flip-flop; setting a gated clock structure clock-gating the flip-flop when the first evaluation value is higher than a first threshold; calculating a second evaluation value indicating the power consumption and a magnitude of a cell area when a low power flip-flop lower in power consumption than the flip-flop is applied to the flip-flop; and replacing the flip-flop by the lower power flip-flop when the second evaluation value is higher than a second threshold.

Developing semiconductor circuit design with conditional flipflops to save power consumption

A clock design apparatus includes a delay time adjusting section, a prohibition specifying section and a clock tree synthesis section. The delay time adjusting section is configured to adjust signal delay time of signal propagation paths on a semiconductor integrated circuit to be designed. The prohibition specifying section is configured to specify a part of the signal propagation paths as a circuit prevented from being changed. The clock tree synthesis section is configured to synthesize a clock tree of the semiconductor integrated circuit in accordance with the specification made by the prohibition specifying section.

Clock design apparatus and clock design method

An automatic circuit design apparatus includes a setting module configured to set an upper limit electric potential of a virtual ground line in a circuit to be designed, by use of a cell library for low-threshold cells, a cell library for high-threshold cells, and information of the circuit to be designed. A layout generator is configured to generate a layout based on the information, the cell library for low-threshold cells, and the cell library for high-threshold cells.

Automatic circuit design apparatus, method for automatically designing a circuit, and computer program product for executing an application for an automatic circuit design apparatus

A computer aided design system and a method for clock gated logic circuits, a computer-readable medium for storing the same and a gated clock circuit are provided in which the clock skew is suppressed within a tolerable level without increasing the electric power consumption.

Computer aided design system and computer-readable medium storing a program for designing clock gated logic circuits and gated clock circuit

An automatic design system for designing wirings on circuit elements, includes an input device configured to receive circuit information, a glitch searching unit configured to search a glitch-occurring circuit element, a skew calculator configured to calculate a skew of a clock signal, a circuit information analyzer configured to define the calculated skew as a first target skew and determine whether the glitch can be reduced by setting the first target, a first target skew setting unit configured to set the first target, and a first latch insertion unit configured to insert a first latch.

Automatic design system for wiring on LSI

A logic circuit design equipment and a logic circuit design method include analyzing input states of all of first cells, respectively, analyzing leakage currents of all of first cells in a case where each first cell is high Vth cell showing a small leakage current at a low speed operation and low Vth cell showing a large leakage current at a high speed operation, respectively, and substituting the first cells for second cells within a range satisfying a timing restriction. Herein, a threshold of the second cell is different from a threshold of the first cell.

Logic circuit design equipment and method for designing logic circuit for reducing leakage current

A computer aided design technique for clock gated logic circuits effective to reduce the electric power consumption is disclosed. The computer aided design for clock gated logic circuits is conducted by extracting, by the use of information about a clock gated logic circuit under the design, a halt condition under which a clocked circuit driven by a clock signal can halt with no clock signal supplied, generating enable signal candidates, from a halt condition, which can be used as enable signals in the clock gated logic circuit, analyzing the clock gated logic circuit in order to obtain information about a delay time of signal transmission and electric power consumption reduction if respective one of enable signal candidates is used as an enable signal of a clock gating circuit inserted in the clock gated logic circuit under the design, storing enable signal candidate information including the result of the analysis conducted by an analysis step in an information store, selecting an appropriate one of the enable signal candidates which satisfy given restrictions regarding a delay time of signal transmission in the clock gated logic circuit under the design, by the use of enable signal candidate information; and adding the clock gating circuit activated with the enable signal as selected by enable signal selection step to the clock gated logic circuit under the design.

Clock supplying circuit and method having enable buffer cells with first and second input terminals

Information about logic circuit not clock-gated, information about enable logic for controlling clock output and information about a gating circuit are inputted through circuit information I/O portion. Enable logic timing constraint generating portion generates timing constraint to be secured for enable logic. Enable logic timing determination portion calculates a delay time in the enable logic and determines whether or not the enable logic satisfies the timing constraint based on the delay time. Clock gating execution portion, when the enable logic satisfies the timing constraint, adds a gating circuit and a circuit composed of the enable logic to a logic circuit not clock-gated so as to generate a clock-gated logic circuit. Circuit information I/O portion outputs information about the clock-gated logic circuit and timing constraint to be secured for the enable logic.

Gated clock design supporting method, gated clock design supporting apparatus, and computer readable memory storing gated clock design supporting program

A computer aided design technique for clock gated logic circuits effective to reduce the electric power consumption is disclosed. The computer aided design for clock gated logic circuits is conducted by extracting, by the use of information about a clock gated logic circuit under the design, a halt condition under which a clocked circuit driven by a clock signal can halt with no clock signal supplied, generating enable signal candidates, from said halt condition, which can be used as enable signals in the clock gated logic circuit, analyzing the clock gated logic circuit in order to obtain information about a delay time of signal transmission and electric power consumption reduction if respective one of enable signal candidates is used as an enable signal of a clock gating circuit inserted in the clock gated logic circuit under the design, storing enable signal candidate information including the result of the analysis conducted by said analysis step in a information store means, selecting an appropriate one of the enable signal candidates which satisfy given restrictions regarding a delay time of signal transmission in the clock gated logic circuit under the design, by the use of said enable signal candidate information; and adding the clock gating circuit activated with the enable signal as selected by said enable signal selection step to the clock gated logic circuit under the design.

Method and apparatus for clock gated logic circuits to reduce electric power consumption

A pair of saddle type horizontal deflection coils are provided at those upper and lower places on the inner wall of the coil separator. Vertical deflection coils toroidally wound on a core are provided on the outer periphery of the coil separator. Neck-side magnetic pieces are provided at those upper and lower sides of the neck-side area between the coil separator on one hand and the vertical deflection coils on the other hand. A pair of magnetic pieces, right and left, are provided, as a pair of crossarms, on the coil separator at a front-side section. In a deflection yoke apparatus thus provided, magnetic field creation areas at the crossarms are provided mainly on a Y axis side and four permanent magnets are provided on the front-side flange section of the coil separator at an angle of about 10.degree. relative to an X axis so that these permanent magnets are magnetized substantially in a tube direction of a CRT.

Deflection yoke apparatus

Disclosed is a test assistant system for a logical design process comprising a description storage data base for storing statements expressing logical functions of circuit components to be tested, a compiler for compiling the statements to output object data, a data base for storing the object data, a test pattern generator for generating test patterns by using the object data stored in the data base, a test pattern data base for storing the test patterns, each having a level number, a simulator for executing a simulation for the logical function by using the test patterns stored in the test pattern data base, and a display for displaying the object data, the test patterns, the information used in the simulation, and relationships among them. The data base comprises a region for storing a statement correspondence table expressing statements as descriptions of the logical functions of the circuit components, a region for storing a circuit component table expressing a circuit component corresponding to the function described in the statement, a region for storing a dependent relationship table expressing the dependent relationship between the statements, and a correspondence relationship table expressing the correspondence relationship between the statement correspondence table and the circuit component table.

Test assistant system for logical design process

Disclosed is a logic synthesis apparatus for automatically composing and designing LSI logic circuits by converting a functional specification based on conversion rules given in advance to the apparatus, which is composed of means for inputting an additional transformation rule, means for executing logic composition of LSI by applying the additional transformation rule to the functional specification preferentially to the conversion rules, and means for revising the conversion rules so as to avoid competition between the conversion rules and the additional transformation rule by analyzing the additional conversion rule, and incorporating the additional transformation rule in the conversion rules, thereby obtaining a learning function to the additional transformation rule.

Growing community of inventors

Kanagawa-ken, Japan

Takeshi Kitahara