Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Takeshi Kishida

Masaitsu Nakajima

Yutaka Yamada

Masanori Hirofuji

Yoshikazu Tamura

Yasuo Sogawa

A data processor includes a first register file including registers, a second register file including registers, a number of which is larger than that of the registers of the first register file, an instruction decoder and an operation unit. The instruction decoder decodes an instruction described in first and second instruction formats. The first instruction format includes a first register-addressing field for designating the first register file. The second instruction format includes a second register-addressing field for designating the second register file, a size of which is larger than that of the first register-addressing field. The operation unit executes an instruction described in the first and second instruction formats using operand data stored in the first and second register files, respectively, based on the instruction decoder, and executes operations in parallel, a number of which is determined by a certain field included in the second instruction format.

Data processor including an operation unit to execute operations in parallel

A data processor which executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file.

Method for instructing a data processor to process data

There is provided a semiconductor device adopting, as a layout of pads connected to an external package on an LSI, a zigzag pad layout in which the pads are arranged shifted alternately, which can avoid occurrences of short-circuiting of wires, an increase in chip size due to avoidance of short-circuiting, propagation of power supply or GND noise due to reduction in IO cell interval, and signal transmission delay difference due to displacement of pad positions. In a semiconductor device wherein plural pads on a semiconductor element which are connected to function terminals on an external package are arranged in two lines along the periphery of the semiconductor element, an arrangement order of the plural pads on the semiconductor element is different from an arrangement order of the function terminals on the external package.

Semiconductor device

A data processor according to the present invention executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file. If the instruction-type identifier has identified the received instruction as being described in the first instruction format, the data processor executes the instruction using data held in the first register file. On the other hand, if the instruction-type identifier has identified the received instruction as being described in the second instruction format, the data processor executes the instruction using data held in the second register file.

Data processor decoding instruction formats using operand data

Data processor

Along with an arithmetic processing unit and an arithmetic execution unit, another arithmetic processing unit is coupled in parallel to an instruction issue unit. Disposed within one of the arithmetic processing units are an address generation unit, an instruction buffer, an instruction decoder, an arithmetic execution unit, a data memory, and a flag register. The instruction decoder decodes an instruction read from the instruction buffer. If the decoded instruction is an iteration start instruction, the instruction decoder extracts a number of times an iterative process is to be executed that is included in the instruction for forwarding to the address generation unit. The address generation unit exerts control as to the execution and termination of iterative processes.

Growing community of inventors

Osaka, Japan

Takeshi Kishida