Sanyo Electric Co., Ltd.

Semiconductor Components Industries, LLC

Sanyo Semiconductor Co., Ltd.

Takeshi Kimura

Tetsuya Tokunaga

Hiroyuki Arai

Syuji Motegi

Shuji Motegi

Takeshi Hibino

Kensuke Goto

Yasuo Osawa

Yoshiyuki Yamagata

Mamoru Yamaguchi

Ryouichi Ando

A data processing circuit comprising: a first circuit configured to time-division-multiplex a first digital signal synchronous with a clock signal input from an external controller and a second digital signal asynchronous with the clock signal; and a second circuit configured to output a digital signal time-division-multiplexed by the first circuit to the controller.

Data processing circuit and data processing method

Increase in power consumption and increase in power supply noise of a serial data input system are suppressed, while clock skew is more easily prevented. The serial data input system of this invention includes a shift register that takes in and shifts serially transferred display data in synchronization with a clock SCL, a clock counter that counts the number of clock pulses of the clock SCL and outputs each of clock count signals BIT, BITand BITwhen the counted number of the clock pulses of the clock SCL reaches each of count numbersandrespectively, and registers into each of which the data stored in the shift register is transferred and stored collectively and in parallel in response to each of the clock count signals BIT, BIPand BITrespectively.

Serial data input system

An interface circuit outputting a clock signal and data to a data register configured to serially read in the data synchronously with the clock signal, in response to a change of a control signal for outputting the clock signal and the data from one logic level to the other logic level, the interface circuit comprising a clock output circuit configured to: detect a logic level of the clock signal when the control signal changes from the one logic level to the other logic level; output the clock signal on an as-is basis to the data register, when detecting one logic level of the clock signal; and output the clock signal after having changed from the other logic level to the one logic level, to the data register, when detecting the other logic level of the clock signal.

Interface circuit and a clock output method therefor

A driving circuit for a vacuum fluorescent display having a filament, a grid electrode and a segment electrode, the driving circuit comprising a filament driving unit for driving the filament; a grid driving unit for pulse-driving the grid electrode; and a segment driving unit for pulse-driving the segment electrode, wherein the driving circuit comprises a controlling unit for validating or invalidating the output of the filament driving unit at a proper timing.

Driving circuit for vacuum fluorescent display

A driving circuit for a vacuum fluorescent display for pulse-driving a filament of the vacuum fluorescent display with a pulse voltage. The driving circuit comprises a detecting unit for detecting that the level of the pulse voltage is fixed, and outputs a detection signal indicative of the result of the detection. Preferably, the driving circuit comprises a control unit for controlling at least one output of the outputs of the filament driving unit, the grid driving unit and the segment driving unit in order to terminate the driving of at least one of the filament, the grid electrode and the segment electrode, based on the detection signal.

A driving circuit for a vacuum fluorescent display having a filament, a grid electrode and a segment electrode, comprising a grid driving unit for pulse-driving the grid electrode, a segment driving unit for pulse-driving the segment electrode, a first controlling unit for rendering adjustable the duty ratio of the output of the grid driving unit, a second controlling unit for rendering adjustable the duty ratio of the output of the segment driving unit, and a selecting unit for selecting the first controlling unit and/or the second controlling unit.

An interface circuit which outputs a clock signal and data to a data register that serially reads in the data synchronously with the clock signal, in response to a control signal changing from one level to the other level, for outputting the clock signal and the data. The interface circuit comprises a clock output circuit that, responding to the level of the clock signal when the control signal changes from the one level to the other level, outputs clocks of the clock signal that are the same in number as bits of the data to the data register.

A frequency adjustment circuit that maintains a target frequency even when frequency adjustment data of zapping circuit is changed by an external noise is offered. The frequency adjustment circuit includes a reset signal generation circuit, a frequency adjustment data latch circuit that latches and retains the frequency adjustment data ZPand ZPgenerated by a first zapping circuit and a second zapping circuit based on a latch clock ZCLK and a latch clock generation circuit that generates the latch clock ZCLK. The reset signal generation circuit generates a periodic reset signal ZRES that is synchronized with a rise of an enable signal EN generated from an interface circuit. The latch clock generation circuit generates the latch clock ZCLK that is synchronized with a fall of the enable signal EN.

Growing community of inventors

Tochigi, Japan

Takeshi Kimura