Hitachi, Ltd.

Hitachi Information Control Systems, Inc.

Hitachi Engineering Co., Ltd.

Takeshi Katoh

Yoshiki Kobayashi

Kotaro Hirasawa

Tadashi Fukushima

Yoshiyuki Okuyama

Noboru Azusawa

Tadashi Okamoto

Makoto Tachikawa

Junichi Hamano

Akihiro Ohhashi

Hitoshi Saitoh

Yasushi Fukunaga

Tadaaki Bandoh

Hiroshi Takenaga

Masataka Kawauchi

Jushi Ide

Seiji Kashioka

Hidekazu Matsumoto

Hiroaki Nakanishi

Kazuyoshi Asada

Shuuichi Miura

Ryosei Hiraoka

Tamio Innami

Yutaka Kubo

Tetsuya Kawakami

Mitsuyoshi Sato

A process controlling method and apparatus which uses a flowchart language program and ladder programs with an intermediate register accessible using the same name by both the flowchart language program and the ladder programs. Each ladder program defines the operation of a machine, including an interlock condition of the machine operation. The flowchart language program defines an automatic operation flow which sequentially activates the ladder programs using the data in the intermediate register. This arrangement allows the flowchart language program to be separated from the ladder programs improving productivity, serviceability and security of the programs.

Apparatus and method for controlling a system process

A process controlling method uses a flowchart language program and ladder programs with an intermediate register to be accessible with the same name by both the flowchart language program and the ladder programs. Each ladder program defines the operation of a machine, including an interlock condition or the like of the machine operation. The flowchart language program defines an automatic operation flow which sequentially activates the ladder programs using the data in the intermediate register. This arrangement allows the flowchart language program to be separated from the ladder programs, thereby improving productivity, serviceability and security of the programs.

An LSI parallel image processor in which line buffers and data-flow switching circuits each requiring a larger amount of hardware in the prior art are incorporated into an LSI circuit, the image data delayed by the line buffers is output from an image data output port, shift registers each having a variable number of steps for preserving local image regions are intermittently shifted-in in accordance with applied clocks, and the contents of the shift registers are sequentially read out.

Parallel image processor for performing local neighboring image

A transacting device performs its transacting operations in response to a customer's request for a deposit or payment transaction. Upon the request for the deposit transaction, paper currencies deposited through a money receiving/paying port are transferred en bloc by paper currency transferring means to an accumulation unit close to a separating unit. The currencies are individually separated by the separating unit and then identified by an identifying unit with respect to authenticity, monetary classification and the number of currencies. Thereafter, the currencies are accumulated in a plurality of accumulation units according to the monetary classification. When making the request for the payment transaction, a plurality of the currencies accumulated in the accumulation units are transferred en bloc by the transferring means to the accumulation unit vicinal to the separating unit. The currencies are separated piece by piece by the separating unit and identified by the identifying unit with respect to the authenticity monetary classification and the number of currencies. The identified currencies are accumulated in another accumulation unit. After the currencies whose species and number are specified by the customer have been accumulated in this accumulation unit, the currencies are transferred en bloc by the transferring means to the money receiving/paying port, whereby the currencies are handed over to the customer.

Transacting device

A peripheral apparatus for image memories can communicate image data with a memory assembly having n blocks of a standard-type DRAM, whether the DRAM is for a page mode or for a nibble mode type operation. The apparatus comprises a read data processing unit sending the data of a selected one among n pixels read from the DRAM blocks in parallel to an external image/graphics processor, a write data processing unit modifying the image data taken thereinto and writing the modified data into the DRAM blocks, a feedback data processing unit writing the image data now on displaying into the DRAM blocks after a desired processing again, a display data processing unit sending the data read from the DRAM blocks to a monitor for display and to the external processor for the feedback processing, and a control unit furnishing control signals to those processing units in response to instructions from the external processer.

Peripheral apparatus for image memories

A multifunctional image processor capable of executing a variety of image processing functions such as a spatial convolution and a color image processing at a higher speed includes an image data distribute unit for distributing the gray-scale and color image data externally supplied by use of programs in accordance with the operation of the image processing and a parallel image data processing unit for conducting a parallel operation on distributed image data in accordance with the operation of the image processing.

Multifunctional image processor

A high speed, multi-function and expandable image processing LSI (image signal processor) for realizing a gray level image processing technique is disclosed. The architecture of the image signal processor can process a gray level image having 256 tones at a video rate (256.times.256 image, 6 MHz, non-interlace), allows expansion of a partial operation area (kernel) and can carry out various partial neighborhood operations. The image signal processor is a partial parallel type image processing LSI which carries out a parallel operation by using the same number of processor elements as that of input pixel data used to produce one output pixel of data.

Image signal processor

A central processing unit for executing instructions of variable length in which an operand specifier for specifying the addressing mode of an operand is independent of an operation code for ascertaining the kind of an operation and the number of operands. Each operand specifier is formed of one or more data bytes, and has a stop bit flag indicating whether or not the particular operand specifier is the last operand specifier. By adding the stop bit flag, the operand specifier can be shared, and different processing can be executed with an identical operation code. In a case where, when operation code decoding means has provided an output indicative of the last operand, the stop bit flat is not detected in the corresponding operand specifier, the corresponding instruction is detected as an error.

Central processing unit for executing instructions of variable length

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Hitachi, Japan

Takeshi Katoh