Nuvoton Technology Corporation Japan

Panasonic Intellectual Property Management Co., Ltd.

Panasonic Semiconductor Solutions Co., Ltd.

Panasonic Corporation

Takeshi Imamura

Kazuma Yoshida

Ryosuke Okawa

Toshikazu Imai

Tsubasa Inoue

Toshihisa Miura

Eiji Yasuda

Shigetoshi Sota

Masaaki Hirako

Ryou Kato

Toshiharu Saito

Yoshinari Nagata

Takashi Ohashi

Mitsuaki Sakamoto

Yasuyuki Masumoto

Tomonari Oota

Hiroki Takeoka

Akihiro Morikawa

Eriko Kanatani

Tomonari Ota

Dohwan Ahn

Satoshi Hosokawa

Yoshiki Kamimura

Wataru Tamura

Hiroto Katsuda

A semiconductor device includes: a semiconductor layer; first and second vertical MOS transistors provided in the semiconductor layer; a metal layer connected to and in contact with an entire surface on a back face side of the semiconductor layer; and a support bonded to a back face side of the metal layer via an adhesive. In a plan view, the support is larger in area than the semiconductor layer and encompasses the semiconductor layer. A thickness of the support is greater than a thickness of the semiconductor layer. In a cross-sectional view, a height of the adhesive along a lateral face of the semiconductor layer does not reach a top face of the semiconductor layer. In the cross-sectional view, a semiconductor chip resulting from excluding the support and the adhesive from the semiconductor device is in a curved shape that projects in a direction toward the support.

Semiconductor device

A semiconductor device includes: a semiconductor layer; first and second vertical MOS transistors provided in the semiconductor layer; a metal layer in contact with and connected to an entire back face of the semiconductor layer; and a support bonded to the back face side of the metal layer via a conductive adhesive. In a plan view, the support is larger in area than the semiconductor layer and encompasses the semiconductor layer. A thickness of the support is greater than a thickness of the semiconductor layer. In a cross-sectional view of the semiconductor device including a center of the semiconductor layer and an outer periphery of the semiconductor layer in the plan view, a semiconductor chip resulting from excluding the support and the conductive adhesive from the semiconductor device is in a curved shape projecting in a direction away from the support.

A capacitor includes a bus bar. The bus bar includes a bus bar body member and a terminal formation member configured to be superposed on and fixed to a terminal formation part of the bus bar body member. In the terminal formation part, a plurality of first connection terminal parts are formed so as to be arranged in one direction, by portions of the terminal formation part being cut and raised. In the terminal formation member, a plurality of second connection terminal parts are formed so as to be arranged in one direction, by portions of the terminal formation member being cut and raised, and second openings are formed in places where the portions have been cut and raised. The first connection terminal parts and the second connection terminal parts are alternately arranged in one direction, by the first connection terminal parts being passed through the second openings.

Capacitor and method for manufacturing capacitor

A semiconductor device includes a first transistor disposed in a first region of a semiconductor layer and a second transistor disposed in a second region of the semiconductor layer, and includes, on the surface of the semiconductor layer, first source pads, a first gate pad, second source pads, and a second gate pad. In the plan view of the semiconductor layer, the first and second transistors are aligned in a first direction; the first gate pad is disposed such that none of the first source pads is disposed between the first gate pad and a side parallel to the first direction and located closest to the first gate pad; and the second gate pad is disposed such that none of the second source pads is disposed between the second gate pad and a side parallel to the first direction and located closest to the second gate pad.

A method for manufacturing a capacitor includes a step of forming a case integrated with a terminal unit designed to be connected with an external terminal, and a step of housing a capacitor element in the case so that the terminal unit is electrically connected to the capacitor element. The step of forming the case includes heating a metal mold to a temperature less than or equal to a glass transition temperature of a thermoplastic resin that is a material for the case. The metal mold internally has a mold part that is a hollow part having a shape of the case. And the step of forming the case further includes, after the heating of the metal mold and inserting the terminal unit into the mold part, injecting the thermoplastic resin in a molten state into the mold part of the metal mold.

Method for manufacturing capacitor

A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors. The thickness of the backside electrode ranges from 25 to 35 &#x3bc;m, and the ratio of the thickness of the backside electrode to the thickness of a semiconductor layer including the semiconductor substrate and the low-concentration impurity layer is 0.32 or more.

Semiconductor device, semiconductor module, and packaged semiconductor device

Growing community of inventors

Kyoto, Japan

Takeshi Imamura