Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Takeshi Hirayama

Takahiro Iwasawa

Keiichi Tsumura

Katsumi Tokuyama

Nobuyuki Minakata

Yoshihisa Shimazu

An image processing device for performing image processing for an image signal output from an image sensor and outputting the results, including: an internal memory having line memories for storing an image by row or column; an image processing section for performing the image processing using the internal memory; and a CPU for controlling the image processing section. The image processing section includes a plurality of processing circuits each performing predetermined processing as the image processing. At least one of the plurality of processing circuits is configured to allow use of an external memory provided outside the image processing device as required.

Image processing device and camera including CPU which determines whether processing performed using external memory

An integrated circuit device is provided which can increase a stable area having less digital noise. A data delay adjustment circuit group () is fed with data outputted from a flip-flop circuit group (), adjusts a delay of the data so as to synchronize the operation of a data output terminal group () with the operation of a logic circuit (), and outputs the data to the data output terminal group (). A clock delay adjustment circuit () similarly adjusts a delay of a clock outputted from an inverter () and outputs the clock to a clock output terminal (). Therefore, the operations of data output terminals are synchronized with the operation of the logic circuit () while keeping the phase relationship between an external output clock and external output data.

Integrated circuit device

A semiconductor integrated circuit device according to the present invention comprises, a semiconductor chip formed with a semiconductor integrated circuit, at least one pair of previous-stage power supply terminals provided on the semiconductor chip and connected to a power supply line, a plurality of pairs of subsequent-stage power supply terminals provided on the semiconductor chip and connected to the power supply line connected commonly to the at least one pair of previous-stage power supply terminals, at least one previous-stage line providing a connection between the at least one pair of previous-stage power supply terminals, and subsequent-stage lines equal in number to the plurality of pairs of subsequent-stage power supply terminals and each providing a connection between the corresponding one of the plurality of pairs of subsequent-stage power supply terminals, wherein the at least one pair of previous-stage power supply terminals and the plurality of pairs of subsequent-stage power supply terminals are connected to each other to form a closed circuit when they are mounted on a mounting board.

Growing community of inventors

Osaka, Japan

Takeshi Hirayama