Kioxia Corporation

Toshiba Memory Corporation

Kabushiki Kaisha Toshiba

Takeshi Hioka

Koji Kato

Hiroshi Maejima

Tsukasa Kobayashi

Yuki Shimizu

Kosuke Yanagidaira

Daisaburo Takashima

Takuyo Kodama

Hiroshi Tsubouchi

Yoshiaki Fukuzumi

Yoshihisa Iwata

Satoshi Inoue

Ryu Ogiwara

Naofumi Abiko

Toshifumi Watanabe

Kensuke Yamamoto

Rui Ito

Yousuke Hagiwara

Mizuki Kaneko

Masaki Unno

A semiconductor storage device includes a plurality of word line layers stacked above one another in a first direction, a memory pillar having a columnar body penetrating the plurality of the word line layers, wherein each portion of the memory pillar intersecting the word line layers functions as a memory cell transistor, a source line layer to which an end of the memory pillar is connected, an acquisition circuit configured to acquire a voltage of the source line layer, and a first adjustment circuit configured to adjust the voltage of the source line layer to a predetermined target voltage based on the acquired voltage. The acquisition circuit includes a dummy pillar having a columnar body penetrating the plurality of word line layers and having an end connected to the source line layer, wherein each portion of the dummy pillar intersecting the word line layers functions as a dummy transistor.

Semiconductor storage device acquiring voltage from dummy pillars

A semiconductor memory device includes first and second memory cell transistors between first and second select transistors, third and fourth memory cell transistors between third and fourth select transistors, a first word line for first and third memory cell transistors, a second word line for second and fourth memory cell transistors, first to fourth selection gate lines respectively for first through fourth select transistors, a bit line, and a source line. During a read operation, while a voltage applied to the second word line is boosted, voltages applied to the first word line and the third and fourth selection gate line are also boosted, after which the voltage applied to the first word line is lowered, and the third and fourth selection gate lines are discharged. After the time the third and fourth selection gate lines are discharged, voltages applied to the bit line and the source line are boosted.

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a memory cell, a word line, a bit line, a first transistor, a second transistor and a driver. The word line is electrically coupled to a gate of the memory cell. The bit line is electrically coupled to one end of the memory cell. The first transistor includes a first gate electrically coupled to the bit line. The second transistor is coupled to a first end of the first transistor. The driver is configured to apply a voltage to the first gate of the first transistor. In a read operation, the driver varies a voltage to be applied to the first gate of the first transistor based on a read voltage applied to the word line.

According to one embodiment, a semiconductor memory device includes first and second memory cells; a first word line connected to the first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a voltage generation circuit; and a first row decoder which supplies a voltage to the first word line.

A semiconductor memory device includes a memory cell array including a plurality of memory cells, a word line connected to the plurality of memory cells, a plurality of bit lines connected respectively to the plurality of memory cells, a sense amplifier connected to the plurality of bit lines, and a controller configured to execute a write operation in a plurality of program loops each including a program operation and a verify operation. The sense amplifier is configured to apply a first voltage, a second voltage higher than the first voltage, a third voltage higher than the second voltage, and a fourth voltage higher than the third voltage to first, second, third, and fourth bit lines of the plurality of bit lines, respectively, while a program voltage is applied to the word line in the program operation.

In general, according to one embodiment, an output circuit includes first to third power supply lines, a pad, first to second transistors, and a first circuit. A first end of the first transistor is coupled to the first power supply line. A second end of the first transistor is coupled to the pad. A first end of the second transistor is coupled to the second power supply line. A second end of the second transistor is coupled to the pad. The first circuit is coupled to each of the third power supply line and a gate of the first transistor. In a first case, the first circuit applies a fourth voltage to the gate of the first transistor.

Output circuit

A semiconductor storage device includes first and second memory cells, first and second word lines connected to the first and second memory cells, respectively, a bit line connected to the first and second memory cells, and a sense amplifier including a sense node. During a first read, a controller applies a first read voltage to the second word line and determines a read result. During a second read, the controller discharges the sense node for a first time period while applying a second read voltage to the first word line to determine a first read result, and discharges the sense node for a second time period while applying the second read voltage to determine a second read result. The controller determines read data based on the first read result, the second read result, and the read result of the second memory cell.

Semiconductor storage device and reading method thereof

A semiconductor storage device includes a plurality of memory cells connected to each other in series, a plurality of word lines respectively connected to gates of the plurality of memory cells, and a control circuit configured to perform a read operation by applying a first voltage higher than ground voltage to the plurality of word lines during a first time period at the beginning of which each word line is at ground voltage, applying a second voltage lower than the first voltage to a first word line during a second time period subsequent to the first time period, applying a third voltage higher than the second voltage to the first word line during a third time period subsequent to the second time period, and determining data of the memory cells connected to the first word line while all portions of the first word line are at the third voltage.

Semiconductor storage device

A semiconductor memory device includes a first memory cell, a first select transistor between the first memory cell and a source line, a second select transistor between the first memory cell and a bit line, a third select transistor between the source line and the bit line, and a control circuit. During an erase operation, the control circuit is configured to apply a first voltage to the source line, apply a second voltage lower than the first voltage to a gate of the third select transistor while applying the first voltage to the source line to cause a third voltage to be applied to the bit line, and apply a fourth voltage lower than the third voltage to the gate of the second select transistor while the third voltage is applied to the bit line.

According to one embodiment, a sense amplifier circuit includes an amplifier having an input terminal connected to a sense node, and a first capacitor configured to be connected in a feedback path of the amplification transistor and to a bit line of a memory cell via the sense node, the first capacitor configured to supply a current to the memory cell and integrate the current when the memory cell is read.

Growing community of inventors

Machida, Japan

Takeshi Hioka